/**
 * @file    gt9881_gpio.h
 * @author  Giantec-Semi ATE
 * @brief   CMSIS GT98xx Device Peripheral Access Layer Header File
 * @version 0.1
 * 
 * @copyright Copyright (c) 2021 Giantec-Semi
 * 
 */

#ifndef GT98XX_DEVICE_GT9881_GPIO_H_
#define GT98XX_DEVICE_GT9881_GPIO_H_

#ifdef __cplusplus
  extern "C" {
#endif /* __cplusplus */

#include "gt9881.h"

/**
 * @addtogroup Peripheral_Registers_Structures
 * @{
 */

/**
 * @struct IOSharingControllerTypedef
 * @brief  MCU IO Sharing Controller Registers structure definition
 */
typedef struct tagIOSharingControllerTypedef {
  __IO uint32_t PIN_FUNC_SEL0;      ///< I/O multiplex function select 0
  __IO uint32_t PIN_FUNC_SEL1;      ///< I/O multiplex function select 1
} IOSharingControllerTypedef;

/**
 * @struct IOCfgTypedef
 * @brief  MCU IO Open Source/Open Drain/Pull Up/Pull Down/Driving Strength/Slew Rate Configuration Registers structure definition
 */
typedef struct tagIOCfgTypedef {
  __IO uint32_t PIN_OS_CTRL;        ///< IO pin open source output mode enable
  __IO uint32_t PIN_OD_CTRL;        ///< Open drain select signal when corresponding I/O pin is used as GPIO pin
  __IO uint32_t PIN_PULLUP_CTRL;    ///< IO pin pull up control
  __IO uint32_t PIN_PULLDOWN_CTRL;  ///< IO pin pull up/pull function disable control
  __IO uint32_t PIN_DS_CTRL;        ///< I/O pin driving strength control
  __IO uint32_t PIN_SL_CTRL;        ///< Ouptut slew rate control for IO pins
} IOCfgTypedef;

/**
 * @struct GpioTypedef
 * @brief GPIO registers structure definition
 */
typedef struct tagGpioTypedef {
  __IO uint32_t DATA;     ///< Data of Input/Output register
  __IO uint32_t DIR;      ///< Direction of data flow register
  __IO uint32_t CTRL;     ///< Control mode select register
  __IO uint32_t EXT;      ///< Port data extend register
  __IO uint32_t IEN;      ///< Interrupt enable register
  __IO uint32_t IS;       ///< Interrupt sense register
  __IO uint32_t IBE;      ///< Interrupt both edge register
  __IO uint32_t IEV;      ///< Interrupt event register
  __IO uint32_t RIS;      ///< Raw interrupt status register
  __IO uint32_t IM;       ///< Interrupt mask register
  __IO uint32_t MIS;      ///< Masked interrupt status register
  __IO uint32_t IC;       ///< Interrupt clear register
  __IO uint32_t DB;       ///< Delete Bounce flag
  __IO uint32_t DFG;      ///< Define Filter-ed Glitch
  __IO uint32_t IG;       ///< Define Interrupt Group
} GpioTypedef;
/** @} Peripheral_Registers_Structures */

/**
 * @addtogroup Peripheral_Memory_Map
 * @{
 */
#define IO_SHARING_CONTROLLER_BASE      (PERIPH_BASE + 0x80UL)           ///< MCU IO Sharing Controller Registers base address
#define MCU_AEN_CTL                     (PERIPH_BASE + 0xA0UL)           ///< MCU IO Analog Enable Register
#define MCU_IO_CFG_BASE                 (PERIPH_BASE + 0xB0UL)           ///< MCU IO Open Source/Open Drain/Pull Up/Pull Down/Driving Strength/Slew Rate Configuration Registers base address
#define GPIO_BASE                       (PERIPH_BASE + 0xB000UL)      ///< GPIO base address
/** @} Peripheral_Memory_Map */

/**
 * @addtogroup Peripheral_Declaration
 * @{
 */
#define IO_SHARING_CONTROLLER     ((IOSharingControllerTypedef*)IO_SHARING_CONTROLLER_BASE)
///< MCU IO Sharing Controller Registers operator
#define MCU_IO_CFG                ((IOCfgTypedef*)MCU_IO_CFG_BASE)
///< MCU IO Open Source/Open Drain/Pull Up/Pull Down/Driving Strength/Slew Rate Configuration Registers operator
#define GPIO                      ((GpioTypedef*)GPIO_BASE)
///< GPIO operator
/** @} Peripheral_Declaration */

/**
 * @defgroup IO_SHARING_CONTROLLER MCU IO Sharing Controller Registers
 * @ingroup  SYSREG
 * @brief    MCU IO Sharing Controller Registers
 * @{
 */

/**
 * @defgroup IO_SHARING_CONTROLLER_BITMAP MCU IO Sharing Controller Bitmap
 * @ingroup  IO_SHARING_CONTROLLER
 * @brief    Bitmap of MCU IO Sharing Controller Registers
 * @{
 */
#define PIN_FUNC_SEL0_SCLK1_Pos                 (0U)    ///< Poision of PIN_FUNC_SEL0_SCLK1
#define PIN_FUNC_SEL0_SCLK1_Msk                 (0x3UL << PIN_FUNC_SEL0_SCLK1_Pos)    ///< Bitmask of PIN_FUNC_SEL0_SCLK1
/**
 * @def   PIN_FUNC_SEL0_SCLK1
 * @brief I/O pin SCLK1 function select.
 * <pre>
 * @a 2'b00 : GPIO[0]
 * @a 2'b01 : Debug_o[0]
 * @a 2'b10 : spim1_clk(0)
 * </pre>
 */
#define PIN_FUNC_SEL0_SCLK1                     PIN_FUNC_SEL0_SCLK1_Msk

#define PIN_FUNC_SEL0_MOSI1_Pos                 (2U)    ///< Poision of PIN_FUNC_SEL0_MOSI1
#define PIN_FUNC_SEL0_MOSI1_Msk                 (0x3UL << PIN_FUNC_SEL0_MOSI1_Pos)    ///< Bitmask of PIN_FUNC_SEL0_MOSI1
/**
 * @def   PIN_FUNC_SEL0_MOSI1
 * @brief I/O pin MOSI1 function select.
 * <pre>
 * @a 2'b00 : GPIO[1]
 * @a 2'b01 : Debug_o[1]
 * @a 2'b10 : spi1_data(io)
 * @a 2'b11 : spi1m_mosi(o)/spi1s_mosi(i)
 * </pre>
 */
#define PIN_FUNC_SEL0_MOSI1                     PIN_FUNC_SEL0_MOSI1_Msk

#define PIN_FUNC_SEL0_MISO1_Pos                 (4U)    ///< Poision of PIN_FUNC_SEL0_MISO1
#define PIN_FUNC_SEL0_MISO1_Msk                 (0x3UL << PIN_FUNC_SEL0_MISO1_Pos)    ///< Bitmask of PIN_FUNC_SEL0_MISO1
/**
 * @def   PIN_FUNC_SEL0_MISO1
 * @brief I/O pin MOSI1 function select.
 * <pre>
 * @a 2'b00 : GPIO[2]
 * @a 2'b01 : Debug_o[2]
 * @a 2'b10 : spi1m_cs(o)
 * @a 2'b11 : spi1m_miso(i) / spi1s_miso(o)
 * </pre>
 */
#define PIN_FUNC_SEL0_MISO1                     PIN_FUNC_SEL0_MISO1_Msk

#define PIN_FUNC_SEL0_SSB1_Pos                  (6U)    ///< Poision of PIN_FUNC_SEL0_SSB1
#define PIN_FUNC_SEL0_SSB1_Msk                  (0x3UL << PIN_FUNC_SEL0_SSB1_Pos)    ///< Bitmask of PIN_FUNC_SEL0_SSB1
/**
 * @def   PIN_FUNC_SEL0_SSB1
 * @brief I/O pin SSB1 function select
 * <pre>
 * @a 2'b00 : GPIO[3]
 * @a 2'b01 : Debug_o[3]
 * @a 2'b10 : spi1m_cs1(o) / spi1s_cs(i)
 * </pre>
 */
#define PIN_FUNC_SEL0_SSB1                      PIN_FUNC_SEL0_SSB1_Msk

#define PIN_FUNC_SEL0_SCLK2_Pos                 (8U)    ///< Poision of PIN_FUNC_SEL0_SCLK2
#define PIN_FUNC_SEL0_SCLK2_Msk                 (0x3UL << PIN_FUNC_SEL0_SCLK2_Pos)    ///< Bitmask of PIN_FUNC_SEL0_SCLK2
/**
 * @def   PIN_FUNC_SEL0_SCLK2
 * @brief I/O pin SCLK2 function select
 * <pre>
 * @a 2'b00 : GPIO[4]
 * @a 2'b01 : Debug_o[4]
 * @a 2'b10 : spi2m_clk(o) / spi2s_clk(i)
 * </pre>
 */
#define PIN_FUNC_SEL0_SCLK2                     PIN_FUNC_SEL0_SCLK2_Msk

#define PIN_FUNC_SEL0_MOSI2_Pos                 (10U)    ///< Poision of PIN_FUNC_SEL0_MOSI2
#define PIN_FUNC_SEL0_MOSI2_Msk                 (0x3UL << PIN_FUNC_SEL0_MOSI2_Pos)    ///< Bitmask of PIN_FUNC_SEL0_MOSI2
/**
 * @def   PIN_FUNC_SEL0_MOSI2
 * @brief I/O pin MOSI2 function select.
 * <pre>
 * @a 2'b00 : GPIO[5]
 * @a 2'b01 : Debug_o[5]
 * @a 2'b10 : spi2_data(io)
 * @a 2'b11 : spi2m_mosi(o) / spi2s_mosi(i)
 * </pre>
 */
#define PIN_FUNC_SEL0_MOSI2                     PIN_FUNC_SEL0_MOSI2_Msk

#define PIN_FUNC_SEL0_MISO2_Pos                 (12U)    ///< Poision of PIN_FUNC_SEL0_MISO2
#define PIN_FUNC_SEL0_MISO2_Msk                 (0x3UL << PIN_FUNC_SEL0_MISO2_Pos)    ///< Bitmask of PIN_FUNC_SEL0_MISO2
/**
 * @def   PIN_FUNC_SEL0_MISO2
 * @brief I/O pin MISO2 function select.
 * <pre>
 * @a 3'b000 : GPIO[6]
 * @a 3'b001 : Debug_o[6]
 * @a 3'b010 : spi2m_cs2(o)
 * @a 3'b011 : spi2m_miso(i) / spi2s_miso(o)
 * @a 3'b100 : uart_tx(o)
 * @a 3'b101 : test_clk_o(o)
 * </pre>
 */
#define PIN_FUNC_SEL0_MISO2                     PIN_FUNC_SEL0_MISO2_Msk

#define PIN_FUNC_SEL0_SSB2_Pos                  (15U)    ///< Poision of PIN_FUNC_SEL0_SSB2
#define PIN_FUNC_SEL0_SSB2_Msk                  (0x7UL << PIN_FUNC_SEL0_SSB2_Pos)    ///< Bitmask of PIN_FUNC_SEL0_SSB2
/**
 * @def   PIN_FUNC_SEL0_SSB2
 * @brief I/O pin SSB2 function select.
 * <pre>
 * @a 3'b000 : GPIO[7]
 * @a 3'b001 : Debug_o[7]
 * @a 3'b010 : spi2m_cs1(o) / spi2s_cs(i)
 * </pre>
 */
#define PIN_FUNC_SEL0_SSB2                      PIN_FUNC_SEL0_SSB2_Msk

#define PIN_FUNC_SEL0_SSB3_Pos                  (18U)    ///< Poision of PIN_FUNC_SEL0_SSB3
#define PIN_FUNC_SEL0_SSB3_Msk                  (0x3UL << PIN_FUNC_SEL0_SSB3_Pos)    ///< Bitmask of PIN_FUNC_SEL0_SSB3
/**
 * @def   PIN_FUNC_SEL0_SSB3
 * @brief I/O pin SSB3 function select.
 * <pre>
 * @a 2'b00 : GPIO[8]
 * @a 2'b01 : Debug_o[8]
 * @a 2'b10 : spi2m_cs3(o)
 * @a 2'b11 : spi1m_cs3(o)
 * </pre>
 */
#define PIN_FUNC_SEL0_SSB3                      PIN_FUNC_SEL0_SSB3_Msk

#define PIN_FUNC_SEL0_ID_Pos                    (20U)    ///< Poision of PIN_FUNC_SEL0_ID
#define PIN_FUNC_SEL0_ID_Msk                    (0x3UL << PIN_FUNC_SEL0_ID_Pos)    ///< Bitmask of PIN_FUNC_SEL0_ID
/**
 * @def   PIN_FUNC_SEL0_ID
 * @brief I/O pin ID function select.
 * <pre>
 * @a 2'b00 : GPIO[9]
 * @a 2'b01 : Debug_o[9]
 * @a 2'b10 : i2c_addr_chg(i)
 * </pre>
 */
#define PIN_FUNC_SEL0_ID                        PIN_FUNC_SEL0_ID_Msk

#define PIN_FUNC_SEL0_SCL2_Pos                  (22U)    ///< Poision of PIN_FUNC_SEL0_SCL2
#define PIN_FUNC_SEL0_SCL2_Msk                  (0x3UL << PIN_FUNC_SEL0_SCL2_Pos)    ///< Bitmask of PIN_FUNC_SEL0_SCL2
/**
 * @def   PIN_FUNC_SEL0_SCL2
 * @brief I/O pin SCL2 function select.
 * <pre>
 * @a 2'b00 : GPIO[10]
 * @a 2'b01 : Debug_o[10]
 * @a 2'b10 : i2c2s_sck(io)
 * @a 2'b11 : uart_tx(o)
 * </pre>
 */
#define PIN_FUNC_SEL0_SCL2                      PIN_FUNC_SEL0_SCL2_Msk

#define PIN_FUNC_SEL0_SDA2_Pos                  (24U)    ///< Poision of PIN_FUNC_SEL0_SDA2
#define PIN_FUNC_SEL0_SDA2_Msk                  (0x3UL << PIN_FUNC_SEL0_SDA2_Pos)    ///< Bitmask of PIN_FUNC_SEL0_SDA2
/**
 * @def   PIN_FUNC_SEL0_SDA2
 * @brief I/O pin SDA2 function select.
 * <pre>
 * @a 2'b00 : GPIO[11]
 * @a 2'b01 : Debug_o[11]
 * @a 2'b10 : i2c2s_sda(io)
 * @a 2'b11 : uart_rx(i)
 * </pre>
 */
#define PIN_FUNC_SEL0_SDA2                      PIN_FUNC_SEL0_SDA2_Msk

#define PIN_FUNC_SEL0_XVS_Pos                   (26U)    ///< Poision of PIN_FUNC_SEL0_XVS
#define PIN_FUNC_SEL0_XVS_Msk                   (0x3UL << PIN_FUNC_SEL0_XVS_Pos)    ///< Bitmask of PIN_FUNC_SEL0_XVS
/**
 * @def   PIN_FUNC_SEL0_XVS
 * @brief I/O pin XVS function select.
 * <pre>
 * @a 2'b00 : GPIO[12]
 * @a 2'b01 : Debug_o[12]
 * @a 2'b10 : exint2(i)
 * @a 2'b11 : xvs(i)
 * </pre>
 */
#define PIN_FUNC_SEL0_XVS                       PIN_FUNC_SEL0_XVS_Msk

#define PIN_FUNC_SEL0_ECLK_Pos                  (28U)    ///< Poision of PIN_FUNC_SEL0_ECLK
#define PIN_FUNC_SEL0_ECLK_Msk                  (0x3UL << PIN_FUNC_SEL0_ECLK_Pos)    ///< Bitmask of PIN_FUNC_SEL0_ECLK
/**
 * @def   PIN_FUNC_SEL0_ECLK
 * @brief I/O pin ECLK function select.
 * <pre>
 * @a 2'b00 : GPIO[13]
 * @a 2'b01 : Debug_o[13]
 * @a 2'b10 : ext_clk(i)
 * @a 2'b11 : swd(io)
 * </pre>
 */
#define PIN_FUNC_SEL0_ECLK                      PIN_FUNC_SEL0_ECLK_Msk

#define PIN_FUNC_SEL1_INT_Pos                   (0U)    ///< Poision of PIN_FUNC_SEL1_INT
#define PIN_FUNC_SEL1_INT_Msk                   (0x7UL << PIN_FUNC_SEL1_INT_Pos)    ///< Bitmask of PIN_FUNC_SEL1_INT
/**
 * @def   PIN_FUNC_SEL1_INT
 * @brief I/O pin INT function select.
 * <pre>
 * @a 3'b000 : GPIO[14]
 * @a 3'b001 : Debug_o[14]
 * @a 3'b010 : exint1(i)
 * @a 3'b011 : swclk(i)
 * @a 3'b100 : pwm_sync(i)
 * </pre>
 */
#define PIN_FUNC_SEL1_INT                       PIN_FUNC_SEL1_INT_Msk

#define PIN_FUNC_SEL1_GPIO0_Pos                   (3U)    ///< Poision of PIN_FUNC_SEL1_GPIO0
#define PIN_FUNC_SEL1_GPIO0_Msk                   (0x3UL << PIN_FUNC_SEL1_GPIO0_Pos)    ///< Bitmask of PIN_FUNC_SEL1_GPIO0
/**
 * @def   PIN_FUNC_SEL1_GPIO0
 * @brief I/O pin GPIO0 function select.
 * <pre>
 * @a 2'b00 : GPIO[15]
 * @a 2'b01 : Debug_o[15]
 * @a 2'b10 : uart_tx(o)
 * </pre>
 */
#define PIN_FUNC_SEL1_GPIO0                       PIN_FUNC_SEL1_GPIO0_Msk

#define PIN_FUNC_SEL1_GPIO1_Pos                   (5U)    ///< Poision of PIN_FUNC_SEL1_GPIO1
#define PIN_FUNC_SEL1_GPIO1_Msk                   (0x3UL << PIN_FUNC_SEL1_GPIO1_Pos)    ///< Bitmask of PIN_FUNC_SEL1_GPIO1
/**
 * @def   PIN_FUNC_SEL1_GPIO1
 * @brief I/O pin GPIO1 function select.
 * <pre>
 * @a 2'b00 : GPIO[16]
 * @a 2'b01 : Debug_o[16]
 * @a 2'b10 : uart_rx(i)
 * </pre>
 */
#define PIN_FUNC_SEL1_GPIO1                       PIN_FUNC_SEL1_GPIO1_Msk

#define PIN_FUNC_SEL1_HLXBO_Pos                   (7U)    ///< Poision of PIN_FUNC_SEL1_HLXBO
#define PIN_FUNC_SEL1_HLXBO_Msk                   (0x1UL << PIN_FUNC_SEL1_HLXBO_Pos)    ///< Bitmask of PIN_FUNC_SEL1_HLXBO
/**
 * @def   PIN_FUNC_SEL1_HLXBO
 * @brief I/O pin HLXBO function select.
 * <pre>
 * @a 1'b0 : GPIO[17]
 * @a 1'b1 : chip_mode_1
 * </pre>
 */
#define PIN_FUNC_SEL1_HLXBO                       PIN_FUNC_SEL1_HLXBO_Msk

#define PIN_FUNC_SEL1_HLYBO_Pos                   (8U)    ///< Poision of PIN_FUNC_SEL1_HLYBO
#define PIN_FUNC_SEL1_HLYBO_Msk                   (0x1UL << PIN_FUNC_SEL1_HLYBO_Pos)    ///< Bitmask of PIN_FUNC_SEL1_HLYBO
/**
 * @def   PIN_FUNC_SEL1_HLYBO
 * @brief I/O pin HLYBO function select.
 * <pre>
 * @a 1'b0 : GPIO[18]
 * @a 1'b1 : chip_mode_2
 * </pre>
 */
#define PIN_FUNC_SEL1_HLYBO                       PIN_FUNC_SEL1_HLYBO_Msk

/** @} IO_SHARING_CONTROLLER_BITMAP */
/** @} IO_SHARING_CONTROLLER */


/**
 * @defgroup IO_ANALOG_ENABLE MCU IO Analog Enable Register
 * @ingroup  SYSREG
 * @brief    MCU IO Analog Enable Register
 * @{
 */

/** @} IO_ANALOG_ENABLE */


/**
 * @defgroup IO_CFG MCU IO Open Source/Open Drain/Pull Up/Pull Down/Driving Strength/Slew Rate Configuration Registers
 * @ingroup  SYSREG
 * @brief    MCU IO Open Source/Open Drain/Pull Up/Pull Down/Driving Strength/Slew Rate Configuration Registers
 * @{
 */

/**
 * @defgroup IO_CFG_BITMAP MCU IO CFG Bitmap
 * @ingroup  IO_CFG
 * @brief    Bitmap of MCU IO CFG
 * @{
 */

#define PIN_OS_CTRL_PAD_SCLK1_Pos                 (0U)    ///< Poision of PIN_OS_CTRL_PAD_SCLK1
#define PIN_OS_CTRL_PAD_SCLK1_Msk                 (0x1UL << PIN_OS_CTRL_PAD_SCLK1_Pos)    ///< Bitmask of PIN_OS_CTRL_PAD_SCLK1
/**
 * @def   PIN_OS_CTRL_PAD_SCLK1
 * @brief IO pin open source output mode enable.
 * <pre>
 * @a 1'b0 : open source output disable
 * @a 1'b1 : open source output enable
 * </pre>
 */
#define PIN_OS_CTRL_PAD_SCLK1                     PIN_OS_CTRL_PAD_SCLK1_Msk

#define PIN_OS_CTRL_PAD_MOSI1_Pos                 (1U)    ///< Poision of PIN_OS_CTRL_PAD_MOSI1
#define PIN_OS_CTRL_PAD_MOSI1_Msk                 (0x1UL << PIN_OS_CTRL_PAD_MOSI1_Pos)    ///< Bitmask of PIN_OS_CTRL_PAD_MOSI1
/**
 * @def   PIN_OS_CTRL_PAD_MOSI1
 * @brief IO pin open source output mode enable.
 * <pre>
 * @a 1'b0 : open source output disable
 * @a 1'b1 : open source output enable
 * </pre>
 */
#define PIN_OS_CTRL_PAD_MOSI1                     PIN_OS_CTRL_PAD_MOSI1_Msk

#define PIN_OS_CTRL_PAD_MISO1_Pos                 (2U)    ///< Poision of PIN_OS_CTRL_PAD_MISO1
#define PIN_OS_CTRL_PAD_MISO1_Msk                 (0x1UL << PIN_OS_CTRL_PAD_MISO1_Pos)    ///< Bitmask of PIN_OS_CTRL_PAD_MISO1
/**
 * @def   PIN_OS_CTRL_PAD_MISO1
 * @brief IO pin open source output mode enable.
 * <pre>
 * @a 1'b0 : open source output disable
 * @a 1'b1 : open source output enable
 * </pre>
 */
#define PIN_OS_CTRL_PAD_MISO1                     PIN_OS_CTRL_PAD_MISO1_Msk

#define PIN_OS_CTRL_PAD_SSB1_Pos                  (3U)    ///< Poision of PIN_OS_CTRL_PAD_SSB1
#define PIN_OS_CTRL_PAD_SSB1_Msk                  (0x1UL << PIN_OS_CTRL_PAD_SSB1_Pos)    ///< Bitmask of PIN_OS_CTRL_PAD_SSB1
/**
 * @def   PIN_OS_CTRL_PAD_SSB1
 * @brief IO pin open source output mode enable.
 * <pre>
 * @a 1'b0 : open source output disable
 * @a 1'b1 : open source output enable
 * </pre>
 */
#define PIN_OS_CTRL_PAD_SSB1                      PIN_OS_CTRL_PAD_SSB1_Msk

#define PIN_OS_CTRL_PAD_SCLK2_Pos                 (4U)    ///< Poision of PIN_OS_CTRL_PAD_SCLK2
#define PIN_OS_CTRL_PAD_SCLK2_Msk                 (0x1UL << PIN_OS_CTRL_PAD_SCLK2_Pos)    ///< Bitmask of PIN_OS_CTRL_PAD_SCLK2
/**
 * @def   PIN_OS_CTRL_PAD_SCLK2
 * @brief IO pin open source output mode enable.
 * <pre>
 * @a 1'b0 : open source output disable
 * @a 1'b1 : open source output enable
 * </pre>
 */
#define PIN_OS_CTRL_PAD_SCLK2                     PIN_OS_CTRL_PAD_SCLK2_Msk

#define PIN_OS_CTRL_PAD_MOSI2_Pos                 (5U)    ///< Poision of PIN_OS_CTRL_PAD_MOSI2
#define PIN_OS_CTRL_PAD_MOSI2_Msk                 (0x1UL << PIN_OS_CTRL_PAD_MOSI2_Pos)    ///< Bitmask of PIN_OS_CTRL_PAD_MOSI2
/**
 * @def   PIN_OS_CTRL_PAD_MOSI2
 * @brief IO pin open source output mode enable.
 * <pre>
 * @a 1'b0 : open source output disable
 * @a 1'b1 : open source output enable
 * </pre>
 */
#define PIN_OS_CTRL_PAD_MOSI2                     PIN_OS_CTRL_PAD_MOSI2_Msk

#define PIN_OS_CTRL_PAD_MISO2_Pos                 (6U)    ///< Poision of PIN_OS_CTRL_PAD_MISO2
#define PIN_OS_CTRL_PAD_MISO2_Msk                 (0x1UL << PIN_OS_CTRL_PAD_MISO2_Pos)    ///< Bitmask of PIN_OS_CTRL_PAD_MISO2
/**
 * @def   PIN_OS_CTRL_PAD_MISO2
 * @brief IO pin open source output mode enable.
 * <pre>
 * @a 1'b0 : open source output disable
 * @a 1'b1 : open source output enable
 * </pre>
 */
#define PIN_OS_CTRL_PAD_MISO2                     PIN_OS_CTRL_PAD_MISO2_Msk

#define PIN_OS_CTRL_PAD_SSB2_Pos                  (7U)    ///< Poision of PIN_OS_CTRL_PAD_SSB2
#define PIN_OS_CTRL_PAD_SSB2_Msk                  (0x1UL << PIN_OS_CTRL_PAD_SSB2_Pos)    ///< Bitmask of PIN_OS_CTRL_PAD_SSB2
/**
 * @def   PIN_OS_CTRL_PAD_SSB2
 * @brief IO pin open source output mode enable.
 * <pre>
 * @a 1'b0 : open source output disable
 * @a 1'b1 : open source output enable
 * </pre>
 */
#define PIN_OS_CTRL_PAD_SSB2                      PIN_OS_CTRL_PAD_SSB2_Msk

#define PIN_OS_CTRL_PAD_SSB3_Pos                  (8U)    ///< Poision of PIN_OS_CTRL_PAD_SSB3
#define PIN_OS_CTRL_PAD_SSB3_Msk                  (0x1UL << PIN_OS_CTRL_PAD_SSB3_Pos)    ///< Bitmask of PIN_OS_CTRL_PAD_SSB3
/**
 * @def   PIN_OS_CTRL_PAD_SSB3
 * @brief IO pin open source output mode enable.
 * <pre>
 * @a 1'b0 : open source output disable
 * @a 1'b1 : open source output enable
 * </pre>
 */
#define PIN_OS_CTRL_PAD_SSB3                      PIN_OS_CTRL_PAD_SSB3_Msk

#define PIN_OS_CTRL_PAD_ID_Pos                    (9U)    ///< Poision of PIN_OS_CTRL_PAD_ID
#define PIN_OS_CTRL_PAD_ID_Msk                    (0x1UL << PIN_OS_CTRL_PAD_ID_Pos)    ///< Bitmask of PIN_OS_CTRL_PAD_ID
/**
 * @def   PIN_OS_CTRL_PAD_ID
 * @brief IO pin open source output mode enable.
 * <pre>
 * @a 1'b0 : open source output disable
 * @a 1'b1 : open source output enable
 * </pre>
 */
#define PIN_OS_CTRL_PAD_ID                        PIN_OS_CTRL_PAD_ID_Msk

#define PIN_OS_CTRL_PAD_SCL1_Pos                  (10U)    ///< Poision of PIN_OS_CTRL_PAD_SCL1
#define PIN_OS_CTRL_PAD_SCL1_Msk                  (0x1UL << PIN_OS_CTRL_PAD_SCL1_Pos)    ///< Bitmask of PIN_OS_CTRL_PAD_SCL1
/**
 * @def   PIN_OS_CTRL_PAD_SCL1
 * @brief IO pin open source output mode enable.
 * <pre>
 * @a 1'b0 : open source output disable
 * @a 1'b1 : open source output enable
 * </pre>
 */
#define PIN_OS_CTRL_PAD_SCL1                      PIN_OS_CTRL_PAD_SCL1_Msk

#define PIN_OS_CTRL_PAD_SDA1_Pos                  (11U)    ///< Poision of PIN_OS_CTRL_PAD_SDA1
#define PIN_OS_CTRL_PAD_SDA1_Msk                  (0x1UL << PIN_OS_CTRL_PAD_SDA1_Pos)    ///< Bitmask of PIN_OS_CTRL_PAD_SDA1
/**
 * @def   PIN_OS_CTRL_PAD_SDA1
 * @brief IO pin open source output mode enable.
 * <pre>
 * @a 1'b0 : open source output disable
 * @a 1'b1 : open source output enable
 * </pre>
 */
#define PIN_OS_CTRL_PAD_SDA1                      PIN_OS_CTRL_PAD_SDS1_Msk

#define PIN_OS_CTRL_PAD_XVS_Pos                   (12U)    ///< Poision of PIN_OS_CTRL_PAD_XVS
#define PIN_OS_CTRL_PAD_XVS_Msk                   (0x1UL << PIN_OS_CTRL_PAD_XVS_Pos)    ///< Bitmask of PIN_OS_CTRL_PAD_XVS
/**
 * @def   PIN_OS_CTRL_PAD_XVS
 * @brief IO pin open source output mode enable.
 * <pre>
 * @a 1'b0 : open source output disable
 * @a 1'b1 : open source output enable
 * </pre>
 */
#define PIN_OS_CTRL_PAD_XVS                       PIN_OS_CTRL_PAD_XVS_Msk

#define PIN_OS_CTRL_PAD_ECLK_Pos                  (13U)    ///< Poision of PIN_OS_CTRL_PAD_ECLK
#define PIN_OS_CTRL_PAD_ECLK_Msk                  (0x1UL << PIN_OS_CTRL_PAD_ECLK_Pos)    ///< Bitmask of PIN_OS_CTRL_PAD_ECLK
/**
 * @def   PIN_OS_CTRL_PAD_ECLK
 * @brief IO pin open source output mode enable.
 * <pre>
 * @a 1'b0 : open source output disable
 * @a 1'b1 : open source output enable
 * </pre>
 */
#define PIN_OS_CTRL_PAD_ECLK                      PIN_OS_CTRL_PAD_ECLK_Msk

#define PIN_OS_CTRL_PAD_INT_Pos                   (14U)    ///< Poision of PIN_OS_CTRL_PAD_INT
#define PIN_OS_CTRL_PAD_INT_Msk                   (0x1UL << PIN_OS_CTRL_PAD_INT_Pos)    ///< Bitmask of PIN_OS_CTRL_PAD_INT
/**
 * @def   PIN_OS_CTRL_PAD_INT
 * @brief IO pin open source output mode enable.
 * <pre>
 * @a 1'b0 : open source output disable
 * @a 1'b1 : open source output enable
 * </pre>
 */
#define PIN_OS_CTRL_PAD_INT                       PIN_OS_CTRL_PAD_INT_Msk

#define PIN_OS_CTRL_PAD_GPIO0_Pos                 (15U)    ///< Poision of PIN_OS_CTRL_PAD_GPIO0
#define PIN_OS_CTRL_PAD_GPIO0_Msk                 (0x1UL << PIN_OS_CTRL_PAD_GPIO0_Pos)    ///< Bitmask of PIN_OS_CTRL_PAD_GPIO0
/**
 * @def   PIN_OS_CTRL_PAD_GPIO0
 * @brief IO pin open source output mode enable.
 * <pre>
 * @a 1'b0 : open source output disable
 * @a 1'b1 : open source output enable
 * </pre>
 */
#define PIN_OS_CTRL_PAD_GPIO0                     PIN_OS_CTRL_PAD_GPIO0_Msk

#define PIN_OS_CTRL_PAD_GPIO1_Pos                 (16U)    ///< Poision of PIN_OS_CTRL_PAD_GPIO1
#define PIN_OS_CTRL_PAD_GPIO1_Msk                 (0x1UL << PIN_OS_CTRL_PAD_GPIO1_Pos)    ///< Bitmask of PIN_OS_CTRL_PAD_GPIO1
/**
 * @def   PIN_OS_CTRL_PAD_GPIO1
 * @brief IO pin open source output mode enable.
 * <pre>
 * @a 1'b0 : open source output disable
 * @a 1'b1 : open source output enable
 * </pre>
 */
#define PIN_OS_CTRL_PAD_GPIO1                     PIN_OS_CTRL_PAD_GPIO1_Msk

#define PIN_OS_CTRL_PAD_HLXBO_Pos                 (17U)    ///< Poision of PIN_OS_CTRL_PAD_HLXBO
#define PIN_OS_CTRL_PAD_HLXBO_Msk                 (0x1UL << PIN_OS_CTRL_PAD_HLXBO_Pos)    ///< Bitmask of PIN_OS_CTRL_PAD_HLXBO
/**
 * @def   PIN_OS_CTRL_PAD_HLXBO
 * @brief IO pin open source output mode enable.
 * <pre>
 * @a 1'b0 : open source output disable
 * @a 1'b1 : open source output enable
 * </pre>
 */
#define PIN_OS_CTRL_PAD_HLXBO                     PIN_OS_CTRL_PAD_HLXBO_Msk

#define PIN_OS_CTRL_PAD_HLYBO_Pos                 (18U)    ///< Poision of PIN_OS_CTRL_PAD_HLYBO
#define PIN_OS_CTRL_PAD_HLYBO_Msk                 (0x1UL << PIN_OS_CTRL_PAD_HLYBO_Pos)    ///< Bitmask of PIN_OS_CTRL_PAD_HLYBO
/**
 * @def   PIN_OS_CTRL_PAD_HLYBO
 * @brief IO pin open source output mode enable.
 * <pre>
 * @a 1'b0 : open source output disable
 * @a 1'b1 : open source output enable
 * </pre>
 */
#define PIN_OS_CTRL_PAD_HLYBO                     PIN_OS_CTRL_PAD_HLYBO_Msk

#define PIN_OD_CTRL_PAD_SCLK1_Pos                 (0U)    ///< Poision of PIN_OD_CTRL_PAD_SCLK1
#define PIN_OD_CTRL_PAD_SCLK1_Msk                 (0x1UL << PIN_OD_CTRL_PAD_SCLK1_Pos)    ///< Bitmask of PIN_OD_CTRL_PAD_SCLK1
/**
 * @def   PIN_OD_CTRL_PAD_SCLK1
 * @brief Open drain select signal when corresponding I/O pin is used as GPIO pin.
 * <pre>
 * @a 1'b0 : normal
 * @a 1'b1 : open drain
 * </pre>
 */
#define PIN_OD_CTRL_PAD_SCLK1                     PIN_OD_CTRL_PAD_SCLK1_Msk

#define PIN_OD_CTRL_PAD_MOSI1_Pos                 (1U)    ///< Poision of PIN_OD_CTRL_PAD_MOSI1
#define PIN_OD_CTRL_PAD_MOSI1_Msk                 (0x1UL << PIN_OD_CTRL_PAD_MOSI1_Pos)    ///< Bitmask of PIN_OD_CTRL_PAD_MOSI1
/**
 * @def   PIN_OD_CTRL_PAD_MOSI1
 * @brief Open drain select signal when corresponding I/O pin is used as GPIO pin.
 * <pre>
 * @a 1'b0 : normal
 * @a 1'b1 : open drain
 * </pre>
 */
#define PIN_OD_CTRL_PAD_MOSI1                     PIN_OD_CTRL_PAD_MOSI1_Msk

#define PIN_OD_CTRL_PAD_MISO1_Pos                 (2U)    ///< Poision of PIN_OD_CTRL_PAD_MISO1
#define PIN_OD_CTRL_PAD_MISO1_Msk                 (0x1UL << PIN_OD_CTRL_PAD_MISO1_Pos)    ///< Bitmask of PIN_OD_CTRL_PAD_MISO1
/**
 * @def   PIN_OD_CTRL_PAD_MISO1
 * @brief Open drain select signal when corresponding I/O pin is used as GPIO pin.
 * <pre>
 * @a 1'b0 : normal
 * @a 1'b1 : open drain
 * </pre>
 */
#define PIN_OD_CTRL_PAD_MISO1                     PIN_OD_CTRL_PAD_MISO1_Msk

#define PIN_OD_CTRL_PAD_SSB1_Pos                  (3U)    ///< Poision of PIN_OD_CTRL_PAD_SSB1
#define PIN_OD_CTRL_PAD_SSB1_Msk                  (0x1UL << PIN_OD_CTRL_PAD_SSB1_Pos)    ///< Bitmask of PIN_OD_CTRL_PAD_SSB1
/**
 * @def   PIN_OD_CTRL_PAD_SSB1
 * @brief Open drain select signal when corresponding I/O pin is used as GPIO pin.
 * <pre>
 * @a 1'b0 : normal
 * @a 1'b1 : open drain
 * </pre>
 */
#define PIN_OD_CTRL_PAD_SSB1                      PIN_OD_CTRL_PAD_SSB1_Msk

#define PIN_OD_CTRL_PAD_SCLK2_Pos                 (4U)    ///< Poision of PIN_OD_CTRL_PAD_SCLK2
#define PIN_OD_CTRL_PAD_SCLK2_Msk                 (0x1UL << PIN_OD_CTRL_PAD_SCLK2_Pos)    ///< Bitmask of PIN_OD_CTRL_PAD_SCLK2
/**
 * @def   PIN_OD_CTRL_PAD_SCLK2
 * @brief Open drain select signal when corresponding I/O pin is used as GPIO pin.
 * <pre>
 * @a 1'b0 : normal
 * @a 1'b1 : open drain
 * </pre>
 */
#define PIN_OD_CTRL_PAD_SCLK2                     PIN_OD_CTRL_PAD_SCLK2_Msk

#define PIN_OD_CTRL_PAD_MOSI2_Pos                 (5U)    ///< Poision of PIN_OD_CTRL_PAD_MOSI2
#define PIN_OD_CTRL_PAD_MOSI2_Msk                 (0x1UL << PIN_OD_CTRL_PAD_MOSI2_Pos)    ///< Bitmask of PIN_OD_CTRL_PAD_MOSI2
/**
 * @def   PIN_OD_CTRL_PAD_MOSI2
 * @brief Open drain select signal when corresponding I/O pin is used as GPIO pin.
 * <pre>
 * @a 1'b0 : normal
 * @a 1'b1 : open drain
 * </pre>
 */
#define PIN_OD_CTRL_PAD_MOSI2                     PIN_OD_CTRL_PAD_MOSI2_Msk

#define PIN_OD_CTRL_PAD_MISO2_Pos                 (6U)    ///< Poision of PIN_OD_CTRL_PAD_MISO2
#define PIN_OD_CTRL_PAD_MISO2_Msk                 (0x1UL << PIN_OD_CTRL_PAD_MISO2_Pos)    ///< Bitmask of PIN_OD_CTRL_PAD_MISO2
/**
 * @def   PIN_OD_CTRL_PAD_MISO2
 * @brief Open drain select signal when corresponding I/O pin is used as GPIO pin.
 * <pre>
 * @a 1'b0 : normal
 * @a 1'b1 : open drain
 * </pre>
 */
#define PIN_OD_CTRL_PAD_MISO2                     PIN_OD_CTRL_PAD_MISO2_Msk

#define PIN_OD_CTRL_PAD_SSB2_Pos                  (7U)    ///< Poision of PIN_OD_CTRL_PAD_SSB2
#define PIN_OD_CTRL_PAD_SSB2_Msk                  (0x1UL << PIN_OD_CTRL_PAD_SSB2_Pos)    ///< Bitmask of PIN_OD_CTRL_PAD_SSB2
/**
 * @def   PIN_OD_CTRL_PAD_SSB2
 * @brief Open drain select signal when corresponding I/O pin is used as GPIO pin.
 * <pre>
 * @a 1'b0 : normal
 * @a 1'b1 : open drain
 * </pre>
 */
#define PIN_OD_CTRL_PAD_SSB2                      PIN_OD_CTRL_PAD_SSB2_Msk

#define PIN_OD_CTRL_PAD_SSB3_Pos                  (8U)    ///< Poision of PIN_OD_CTRL_PAD_SSB3
#define PIN_OD_CTRL_PAD_SSB3_Msk                  (0x1UL << PIN_OD_CTRL_PAD_SSB3_Pos)    ///< Bitmask of PIN_OD_CTRL_PAD_SSB3
/**
 * @def   PIN_OD_CTRL_PAD_SSB3
 * @brief Open drain select signal when corresponding I/O pin is used as GPIO pin.
 * <pre>
 * @a 1'b0 : normal
 * @a 1'b1 : open drain
 * </pre>
 */
#define PIN_OD_CTRL_PAD_SSB3                      PIN_OD_CTRL_PAD_SSB3_Msk

#define PIN_OD_CTRL_PAD_ID_Pos                    (9U)    ///< Poision of PIN_OD_CTRL_PAD_ID
#define PIN_OD_CTRL_PAD_ID_Msk                    (0x1UL << PIN_OD_CTRL_PAD_ID_Pos)    ///< Bitmask of PIN_OD_CTRL_PAD_ID
/**
 * @def   PIN_OD_CTRL_PAD_ID
 * @brief Open drain select signal when corresponding I/O pin is used as GPIO pin.
 * <pre>
 * @a 1'b0 : normal
 * @a 1'b1 : open drain
 * </pre>
 */
#define PIN_OD_CTRL_PAD_ID                        PIN_OD_CTRL_PAD_ID_Msk

#define PIN_OD_CTRL_PAD_SCL1_Pos                  (10U)    ///< Poision of PIN_OD_CTRL_PAD_SCL1
#define PIN_OD_CTRL_PAD_SCL1_Msk                  (0x1UL << PIN_OD_CTRL_PAD_SCL1_Pos)    ///< Bitmask of PIN_OD_CTRL_PAD_SCL1
/**
 * @def   PIN_OD_CTRL_PAD_SCL1
 * @brief Open drain select signal when corresponding I/O pin is used as GPIO pin.
 * <pre>
 * @a 1'b0 : normal
 * @a 1'b1 : open drain
 * </pre>
 */
#define PIN_OD_CTRL_PAD_SCL1                      PIN_OD_CTRL_PAD_SCL1_Msk

#define PIN_OD_CTRL_PAD_SDA1_Pos                  (11U)    ///< Poision of PIN_OD_CTRL_PAD_SDA1
#define PIN_OD_CTRL_PAD_SDA1_Msk                  (0x1UL << PIN_OD_CTRL_PAD_SDA1_Pos)    ///< Bitmask of PIN_OD_CTRL_PAD_SDA1
/**
 * @def   PIN_OD_CTRL_PAD_SDA1
 * @brief Open drain select signal when corresponding I/O pin is used as GPIO pin.
 * <pre>
 * @a 1'b0 : normal
 * @a 1'b1 : open drain
 * </pre>
 */
#define PIN_OD_CTRL_PAD_SDA1                      PIN_OD_CTRL_PAD_SDS1_Msk

#define PIN_OD_CTRL_PAD_XVS_Pos                   (12U)    ///< Poision of PIN_OD_CTRL_PAD_XVS
#define PIN_OD_CTRL_PAD_XVS_Msk                   (0x1UL << PIN_OD_CTRL_PAD_XVS_Pos)    ///< Bitmask of PIN_OD_CTRL_PAD_XVS
/**
 * @def   PIN_OD_CTRL_PAD_XVS
 * @brief Open drain select signal when corresponding I/O pin is used as GPIO pin.
 * <pre>
 * @a 1'b0 : normal
 * @a 1'b1 : open drain
 * </pre>
 */
#define PIN_OD_CTRL_PAD_XVS                       PIN_OD_CTRL_PAD_XVS_Msk

#define PIN_OD_CTRL_PAD_ECLK_Pos                  (13U)    ///< Poision of PIN_OD_CTRL_PAD_ECLK
#define PIN_OD_CTRL_PAD_ECLK_Msk                  (0x1UL << PIN_OD_CTRL_PAD_ECLK_Pos)    ///< Bitmask of PIN_OD_CTRL_PAD_ECLK
/**
 * @def   PIN_OD_CTRL_PAD_ECLK
 * @brief Open drain select signal when corresponding I/O pin is used as GPIO pin.
 * <pre>
 * @a 1'b0 : normal
 * @a 1'b1 : open drain
 * </pre>
 */
#define PIN_OD_CTRL_PAD_ECLK                      PIN_OD_CTRL_PAD_ECLK_Msk

#define PIN_OD_CTRL_PAD_INT_Pos                   (14U)    ///< Poision of PIN_OD_CTRL_PAD_INT
#define PIN_OD_CTRL_PAD_INT_Msk                   (0x1UL << PIN_OD_CTRL_PAD_INT_Pos)    ///< Bitmask of PIN_OD_CTRL_PAD_INT
/**
 * @def   PIN_OD_CTRL_PAD_INT
 * @brief Open drain select signal when corresponding I/O pin is used as GPIO pin.
 * <pre>
 * @a 1'b0 : normal
 * @a 1'b1 : open drain
 * </pre>
 */
#define PIN_OD_CTRL_PAD_INT                       PIN_OD_CTRL_PAD_INT_Msk

#define PIN_OD_CTRL_PAD_GPIO0_Pos                 (15U)    ///< Poision of PIN_OD_CTRL_PAD_GPIO0
#define PIN_OD_CTRL_PAD_GPIO0_Msk                 (0x1UL << PIN_OD_CTRL_PAD_GPIO0_Pos)    ///< Bitmask of PIN_OD_CTRL_PAD_GPIO0
/**
 * @def   PIN_OD_CTRL_PAD_GPIO0
 * @brief Open drain select signal when corresponding I/O pin is used as GPIO pin.
 * <pre>
 * @a 1'b0 : normal
 * @a 1'b1 : open drain
 * </pre>
 */
#define PIN_OD_CTRL_PAD_GPIO0                     PIN_OD_CTRL_PAD_GPIO0_Msk

#define PIN_OD_CTRL_PAD_GPIO1_Pos                 (16U)    ///< Poision of PIN_OD_CTRL_PAD_GPIO1
#define PIN_OD_CTRL_PAD_GPIO1_Msk                 (0x1UL << PIN_OD_CTRL_PAD_GPIO1_Pos)    ///< Bitmask of PIN_OD_CTRL_PAD_GPIO1
/**
 * @def   PIN_OD_CTRL_PAD_GPIO1
 * @brief Open drain select signal when corresponding I/O pin is used as GPIO pin.
 * <pre>
 * @a 1'b0 : normal
 * @a 1'b1 : open drain
 * </pre>
 */
#define PIN_OD_CTRL_PAD_GPIO1                     PIN_OD_CTRL_PAD_GPIO1_Msk

#define PIN_OD_CTRL_PAD_HLXBO_Pos                 (17U)    ///< Poision of PIN_OD_CTRL_PAD_HLXBO
#define PIN_OD_CTRL_PAD_HLXBO_Msk                 (0x1UL << PIN_OD_CTRL_PAD_HLXBO_Pos)    ///< Bitmask of PIN_OD_CTRL_PAD_HLXBO
/**
 * @def   PIN_OD_CTRL_PAD_HLXBO
 * @brief Open drain select signal when corresponding I/O pin is used as GPIO pin.
 * <pre>
 * @a 1'b0 : normal
 * @a 1'b1 : open drain
 * </pre>
 */
#define PIN_OD_CTRL_PAD_HLXBO                     PIN_OD_CTRL_PAD_HLXBO_Msk

#define PIN_OD_CTRL_PAD_HLYBO_Pos                 (18U)    ///< Poision of PIN_OD_CTRL_PAD_HLYBO
#define PIN_OD_CTRL_PAD_HLYBO_Msk                 (0x1UL << PIN_OD_CTRL_PAD_HLYBO_Pos)    ///< Bitmask of PIN_OD_CTRL_PAD_HLYBO
/**
 * @def   PIN_OD_CTRL_PAD_HLYBO
 * @brief Open drain select signal when corresponding I/O pin is used as GPIO pin.
 * <pre>
 * @a 1'b0 : normal
 * @a 1'b1 : open drain
 * </pre>
 */
#define PIN_OD_CTRL_PAD_HLYBO                     PIN_OD_CTRL_PAD_HLYBO_Msk

#define PIN_PULLUP_CTRL_PAD_SCLK1_Pos             (0U)    ///< Poision of PIN_PULLUP_CTRL_PAD_SCLK1
#define PIN_PULLUP_CTRL_PAD_SCLK1_Msk             (0x1UL << PIN_PULLUP_CTRL_PAD_SCLK1_Pos)    ///< Bitmask of PIN_PULLUP_CTRL_PAD_SCLK1
/**
 * @def   PIN_PULLUP_CTRL_PAD_SCLK1
 * @brief IO pin pull up control.
 * <pre>
 * @a 1'b0 : pull up is disable
 * @a 1'b1 : pull up is enable
 * </pre>
 */
#define PIN_PULLUP_CTRL_PAD_SCLK1                 PIN_PULLUP_CTRL_PAD_SCLK1_Msk

#define PIN_PULLUP_CTRL_PAD_MOSI1_Pos             (1U)    ///< Poision of PIN_PULLUP_CTRL_PAD_MOSI1
#define PIN_PULLUP_CTRL_PAD_MOSI1_Msk             (0x1UL << PIN_PULLUP_CTRL_PAD_MOSI1_Pos)    ///< Bitmask of PIN_PULLUP_CTRL_PAD_MOSI1
/**
 * @def   PIN_PULLUP_CTRL_PAD_MOSI1
 * @brief IO pin pull up control.
 * <pre>
 * @a 1'b0 : pull up is disable
 * @a 1'b1 : pull up is enable
 * </pre>
 */
#define PIN_PULLUP_CTRL_PAD_MOSI1                 PIN_PULLUP_CTRL_PAD_MOSI1_Msk

#define PIN_PULLUP_CTRL_PAD_MISO1_Pos             (2U)    ///< Poision of PIN_PULLUP_CTRL_PAD_MISO1
#define PIN_PULLUP_CTRL_PAD_MISO1_Msk             (0x1UL << PIN_PULLUP_CTRL_PAD_MISO1_Pos)    ///< Bitmask of PIN_PULLUP_CTRL_PAD_MISO1
/**
 * @def   PIN_PULLUP_CTRL_PAD_MISO1
 * @brief IO pin pull up control.
 * <pre>
 * @a 1'b0 : pull up is disable
 * @a 1'b1 : pull up is enable
 * </pre>
 */
#define PIN_PULLUP_CTRL_PAD_MISO1                 PIN_PULLUP_CTRL_PAD_MISO1_Msk

#define PIN_PULLUP_CTRL_PAD_SSB1_Pos              (3U)    ///< Poision of PIN_PULLUP_CTRL_PAD_SSB1
#define PIN_PULLUP_CTRL_PAD_SSB1_Msk              (0x1UL << PIN_PULLUP_CTRL_PAD_SSB1_Pos)    ///< Bitmask of PIN_PULLUP_CTRL_PAD_SSB1
/**
 * @def   PIN_PULLUP_CTRL_PAD_SSB1
 * @brief IO pin pull up control.
 * <pre>
 * @a 1'b0 : pull up is disable
 * @a 1'b1 : pull up is enable
 * </pre>
 */
#define PIN_PULLUP_CTRL_PAD_SSB1                  PIN_PULLUP_CTRL_PAD_SSB1_Msk

#define PIN_PULLUP_CTRL_PAD_SCLK2_Pos             (4U)    ///< Poision of PIN_PULLUP_CTRL_PAD_SCLK2
#define PIN_PULLUP_CTRL_PAD_SCLK2_Msk             (0x1UL << PIN_PULLUP_CTRL_PAD_SCLK2_Pos)    ///< Bitmask of PIN_PULLUP_CTRL_PAD_SCLK2
/**
 * @def   PIN_PULLUP_CTRL_PAD_SCLK2
 * @brief IO pin pull up control.
 * <pre>
 * @a 1'b0 : pull up is disable
 * @a 1'b1 : pull up is enable
 * </pre>
 */
#define PIN_PULLUP_CTRL_PAD_SCLK2                 PIN_PULLUP_CTRL_PAD_SCLK2_Msk

#define PIN_PULLUP_CTRL_PAD_MOSI2_Pos             (5U)    ///< Poision of PIN_PULLUP_CTRL_PAD_MOSI2
#define PIN_PULLUP_CTRL_PAD_MOSI2_Msk             (0x1UL << PIN_PULLUP_CTRL_PAD_MOSI2_Pos)    ///< Bitmask of PIN_PULLUP_CTRL_PAD_MOSI2
/**
 * @def   PIN_PULLUP_CTRL_PAD_MOSI2
 * @brief IO pin pull up control.
 * <pre>
 * @a 1'b0 : pull up is disable
 * @a 1'b1 : pull up is enable
 * </pre>
 */
#define PIN_PULLUP_CTRL_PAD_MOSI2                 PIN_PULLUP_CTRL_PAD_MOSI2_Msk

#define PIN_PULLUP_CTRL_PAD_MISO2_Pos             (6U)    ///< Poision of PIN_PULLUP_CTRL_PAD_MISO2
#define PIN_PULLUP_CTRL_PAD_MISO2_Msk             (0x1UL << PIN_PULLUP_CTRL_PAD_MISO2_Pos)    ///< Bitmask of PIN_PULLUP_CTRL_PAD_MISO2
/**
 * @def   PIN_PULLUP_CTRL_PAD_MISO2
 * @brief IO pin pull up control.
 * <pre>
 * @a 1'b0 : pull up is disable
 * @a 1'b1 : pull up is enable
 * </pre>
 */
#define PIN_PULLUP_CTRL_PAD_MISO2                 PIN_PULLUP_CTRL_PAD_MISO2_Msk

#define PIN_PULLUP_CTRL_PAD_SSB2_Pos              (7U)    ///< Poision of PIN_PULLUP_CTRL_PAD_SSB2
#define PIN_PULLUP_CTRL_PAD_SSB2_Msk              (0x1UL << PIN_PULLUP_CTRL_PAD_SSB2_Pos)    ///< Bitmask of PIN_PULLUP_CTRL_PAD_SSB2
/**
 * @def   PIN_PULLUP_CTRL_PAD_SSB2
 * @brief IO pin pull up control.
 * <pre>
 * @a 1'b0 : pull up is disable
 * @a 1'b1 : pull up is enable
 * </pre>
 */
#define PIN_PULLUP_CTRL_PAD_SSB2                  PIN_PULLUP_CTRL_PAD_SSB2_Msk

#define PIN_PULLUP_CTRL_PAD_SSB3_Pos              (8U)    ///< Poision of PIN_PULLUP_CTRL_PAD_SSB3
#define PIN_PULLUP_CTRL_PAD_SSB3_Msk              (0x1UL << PIN_PULLUP_CTRL_PAD_SSB3_Pos)    ///< Bitmask of PIN_PULLUP_CTRL_PAD_SSB3
/**
 * @def   PIN_PULLUP_CTRL_PAD_SSB3
 * @brief IO pin pull up control.
 * <pre>
 * @a 1'b0 : pull up is disable
 * @a 1'b1 : pull up is enable
 * </pre>
 */
#define PIN_PULLUP_CTRL_PAD_SSB3                  PIN_PULLUP_CTRL_PAD_SSB3_Msk

#define PIN_PULLUP_CTRL_PAD_ID_Pos                (9U)    ///< Poision of PIN_PULLUP_CTRL_PAD_ID
#define PIN_PULLUP_CTRL_PAD_ID_Msk                (0x1UL << PIN_PULLUP_CTRL_PAD_ID_Pos)    ///< Bitmask of PIN_PULLUP_CTRL_PAD_ID
/**
 * @def   PIN_PULLUP_CTRL_PAD_ID
 * @brief IO pin pull up control.
 * <pre>
 * @a 1'b0 : pull up is disable
 * @a 1'b1 : pull up is enable
 * </pre>
 */
#define PIN_PULLUP_CTRL_PAD_ID                    PIN_PULLUP_CTRL_PAD_ID_Msk

#define PIN_PULLUP_CTRL_PAD_SCL1_Pos              (10U)    ///< Poision of PIN_PULLUP_CTRL_PAD_SCL1
#define PIN_PULLUP_CTRL_PAD_SCL1_Msk              (0x1UL << PIN_PULLUP_CTRL_PAD_SCL1_Pos)    ///< Bitmask of PIN_PULLUP_CTRL_PAD_SCL1
/**
 * @def   PIN_PULLUP_CTRL_PAD_SCL1
 * @brief IO pin pull up control.
 * <pre>
 * @a 1'b0 : pull up is disable
 * @a 1'b1 : pull up is enable
 * </pre>
 */
#define PIN_PULLUP_CTRL_PAD_SCL1                  PIN_PULLUP_CTRL_PAD_SCL1_Msk

#define PIN_PULLUP_CTRL_PAD_SDA1_Pos              (11U)    ///< Poision of PIN_PULLUP_CTRL_PAD_SDA1
#define PIN_PULLUP_CTRL_PAD_SDA1_Msk              (0x1UL << PIN_PULLUP_CTRL_PAD_SDA1_Pos)    ///< Bitmask of PIN_PULLUP_CTRL_PAD_SDA1
/**
 * @def   PIN_PULLUP_CTRL_PAD_SDA1
 * @brief IO pin pull up control.
 * <pre>
 * @a 1'b0 : pull up is disable
 * @a 1'b1 : pull up is enable
 * </pre>
 */
#define PIN_PULLUP_CTRL_PAD_SDA1                  PIN_PULLUP_CTRL_PAD_SDS1_Msk

#define PIN_PULLUP_CTRL_PAD_XVS_Pos               (12U)    ///< Poision of PIN_PULLUP_CTRL_PAD_XVS
#define PIN_PULLUP_CTRL_PAD_XVS_Msk               (0x1UL << PIN_PULLUP_CTRL_PAD_XVS_Pos)    ///< Bitmask of PIN_PULLUP_CTRL_PAD_XVS
/**
 * @def   PIN_PULLUP_CTRL_PAD_XVS
 * @brief IO pin pull up control.
 * <pre>
 * @a 1'b0 : pull up is disable
 * @a 1'b1 : pull up is enable
 * </pre>
 */
#define PIN_PULLUP_CTRL_PAD_XVS                   PIN_PULLUP_CTRL_PAD_XVS_Msk

#define PIN_PULLUP_CTRL_PAD_ECLK_Pos              (13U)    ///< Poision of PIN_PULLUP_CTRL_PAD_ECLK
#define PIN_PULLUP_CTRL_PAD_ECLK_Msk              (0x1UL << PIN_PULLUP_CTRL_PAD_ECLK_Pos)    ///< Bitmask of PIN_PULLUP_CTRL_PAD_ECLK
/**
 * @def   PIN_PULLUP_CTRL_PAD_ECLK
 * @brief IO pin pull up control.
 * <pre>
 * @a 1'b0 : pull up is disable
 * @a 1'b1 : pull up is enable
 * </pre>
 */
#define PIN_PULLUP_CTRL_PAD_ECLK                  PIN_PULLUP_CTRL_PAD_ECLK_Msk

#define PIN_PULLUP_CTRL_PAD_INT_Pos               (14U)    ///< Poision of PIN_PULLUP_CTRL_PAD_INT
#define PIN_PULLUP_CTRL_PAD_INT_Msk               (0x1UL << PIN_PULLUP_CTRL_PAD_INT_Pos)    ///< Bitmask of PIN_PULLUP_CTRL_PAD_INT
/**
 * @def   PIN_PULLUP_CTRL_PAD_INT
 * @brief IO pin pull up control.
 * <pre>
 * @a 1'b0 : pull up is disable
 * @a 1'b1 : pull up is enable
 * </pre>
 */
#define PIN_PULLUP_CTRL_PAD_INT                   PIN_PULLUP_CTRL_PAD_INT_Msk

#define PIN_PULLUP_CTRL_PAD_GPIO0_Pos             (15U)    ///< Poision of PIN_PULLUP_CTRL_PAD_GPIO0
#define PIN_PULLUP_CTRL_PAD_GPIO0_Msk             (0x1UL << PIN_PULLUP_CTRL_PAD_GPIO0_Pos)    ///< Bitmask of PIN_PULLUP_CTRL_PAD_GPIO0
/**
 * @def   PIN_PULLUP_CTRL_PAD_GPIO0
 * @brief IO pin pull up control.
 * <pre>
 * @a 1'b0 : pull up is disable
 * @a 1'b1 : pull up is enable
 * </pre>
 */
#define PIN_PULLUP_CTRL_PAD_GPIO0                 PIN_PULLUP_CTRL_PAD_GPIO0_Msk

#define PIN_PULLUP_CTRL_PAD_GPIO1_Pos             (16U)    ///< Poision of PIN_PULLUP_CTRL_PAD_GPIO1
#define PIN_PULLUP_CTRL_PAD_GPIO1_Msk             (0x1UL << PIN_PULLUP_CTRL_PAD_GPIO1_Pos)    ///< Bitmask of PIN_PULLUP_CTRL_PAD_GPIO1
/**
 * @def   PIN_PULLUP_CTRL_PAD_GPIO1
 * @brief IO pin pull up control.
 * <pre>
 * @a 1'b0 : pull up is disable
 * @a 1'b1 : pull up is enable
 * </pre>
 */
#define PIN_PULLUP_CTRL_PAD_GPIO1                 PIN_PULLUP_CTRL_PAD_GPIO1_Msk

#define PIN_PULLUP_CTRL_PAD_HLXBO_Pos             (17U)    ///< Poision of PIN_PULLUP_CTRL_PAD_HLXBO
#define PIN_PULLUP_CTRL_PAD_HLXBO_Msk             (0x1UL << PIN_PULLUP_CTRL_PAD_HLXBO_Pos)    ///< Bitmask of PIN_PULLUP_CTRL_PAD_HLXBO
/**
 * @def   PIN_PULLUP_CTRL_PAD_HLXBO
 * @brief IO pin pull up control.
 * <pre>
 * @a 1'b0 : pull up is disable
 * @a 1'b1 : pull up is enable
 * </pre>
 */
#define PIN_PULLUP_CTRL_PAD_HLXBO                 PIN_PULLUP_CTRL_PAD_HLXBO_Msk

#define PIN_PULLUP_CTRL_PAD_HLYBO_Pos             (18U)    ///< Poision of PIN_PULLUP_CTRL_PAD_HLYBO
#define PIN_PULLUP_CTRL_PAD_HLYBO_Msk             (0x1UL << PIN_PULLUP_CTRL_PAD_HLYBO_Pos)    ///< Bitmask of PIN_PULLUP_CTRL_PAD_HLYBO
/**
 * @def   PIN_PULLUP_CTRL_PAD_HLYBO
 * @brief IO pin pull up control.
 * <pre>
 * @a 1'b0 : pull up is disable
 * @a 1'b1 : pull up is enable
 * </pre>
 */
#define PIN_PULLUP_CTRL_PAD_HLYBO                 PIN_PULLUP_CTRL_PAD_HLYBO_Msk

#define PIN_PULLDOWN_CTRL_PAD_SCLK1_Pos           (0U)    ///< Poision of PIN_PULLDOWN_CTRL_PAD_SCLK1
#define PIN_PULLDOWN_CTRL_PAD_SCLK1_Msk           (0x1UL << PIN_PULLDOWN_CTRL_PAD_SCLK1_Pos)    ///< Bitmask of PIN_PULLDOWN_CTRL_PAD_SCLK1
/**
 * @def   PIN_PULLDOWN_CTRL_PAD_SCLK1
 * @brief IO pin pull up/pull function disable control.
 * <pre>
 * @a 1'b0 : pull down is disable
 * @a 1'b1 : pull down is enable
 * </pre>
 */
#define PIN_PULLDOWN_CTRL_PAD_SCLK1               PIN_PULLDOWN_CTRL_PAD_SCLK1_Msk

#define PIN_PULLDOWN_CTRL_PAD_MOSI1_Pos           (1U)    ///< Poision of PIN_PULLDOWN_CTRL_PAD_MOSI1
#define PIN_PULLDOWN_CTRL_PAD_MOSI1_Msk           (0x1UL << PIN_PULLDOWN_CTRL_PAD_MOSI1_Pos)    ///< Bitmask of PIN_PULLDOWN_CTRL_PAD_MOSI1
/**
 * @def   PIN_PULLDOWN_CTRL_PAD_MOSI1
 * @brief IO pin pull up/pull function disable control.
 * <pre>
 * @a 1'b0 : pull down is disable
 * @a 1'b1 : pull down is enable
 * </pre>
 */
#define PIN_PULLDOWN_CTRL_PAD_MOSI1               PIN_PULLDOWN_CTRL_PAD_MOSI1_Msk

#define PIN_PULLDOWN_CTRL_PAD_MISO1_Pos           (2U)    ///< Poision of PIN_PULLDOWN_CTRL_PAD_MISO1
#define PIN_PULLDOWN_CTRL_PAD_MISO1_Msk           (0x1UL << PIN_PULLDOWN_CTRL_PAD_MISO1_Pos)    ///< Bitmask of PIN_PULLDOWN_CTRL_PAD_MISO1
/**
 * @def   PIN_PULLDOWN_CTRL_PAD_MISO1
 * @brief IO pin pull up/pull function disable control.
 * <pre>
 * @a 1'b0 : pull down is disable
 * @a 1'b1 : pull down is enable
 * </pre>
 */
#define PIN_PULLDOWN_CTRL_PAD_MISO1               PIN_PULLDOWN_CTRL_PAD_MISO1_Msk

#define PIN_PULLDOWN_CTRL_PAD_SSB1_Pos            (3U)    ///< Poision of PIN_PULLDOWN_CTRL_PAD_SSB1
#define PIN_PULLDOWN_CTRL_PAD_SSB1_Msk            (0x1UL << PIN_PULLDOWN_CTRL_PAD_SSB1_Pos)    ///< Bitmask of PIN_PULLDOWN_CTRL_PAD_SSB1
/**
 * @def   PIN_PULLDOWN_CTRL_PAD_SSB1
 * @brief IO pin pull up/pull function disable control.
 * <pre>
 * @a 1'b0 : pull down is disable
 * @a 1'b1 : pull down is enable
 * </pre>
 */
#define PIN_PULLDOWN_CTRL_PAD_SSB1                PIN_PULLDOWN_CTRL_PAD_SSB1_Msk

#define PIN_PULLDOWN_CTRL_PAD_SCLK2_Pos           (4U)    ///< Poision of PIN_PULLDOWN_CTRL_PAD_SCLK2
#define PIN_PULLDOWN_CTRL_PAD_SCLK2_Msk           (0x1UL << PIN_PULLDOWN_CTRL_PAD_SCLK2_Pos)    ///< Bitmask of PIN_PULLDOWN_CTRL_PAD_SCLK2
/**
 * @def   PIN_PULLDOWN_CTRL_PAD_SCLK2
 * @brief IO pin pull up/pull function disable control.
 * <pre>
 * @a 1'b0 : pull down is disable
 * @a 1'b1 : pull down is enable
 * </pre>
 */
#define PIN_PULLDOWN_CTRL_PAD_SCLK2               PIN_PULLDOWN_CTRL_PAD_SCLK2_Msk

#define PIN_PULLDOWN_CTRL_PAD_MOSI2_Pos           (5U)    ///< Poision of PIN_PULLDOWN_CTRL_PAD_MOSI2
#define PIN_PULLDOWN_CTRL_PAD_MOSI2_Msk           (0x1UL << PIN_PULLDOWN_CTRL_PAD_MOSI2_Pos)    ///< Bitmask of PIN_PULLDOWN_CTRL_PAD_MOSI2
/**
 * @def   PIN_PULLDOWN_CTRL_PAD_MOSI2
 * @brief IO pin pull up/pull function disable control.
 * <pre>
 * @a 1'b0 : pull down is disable
 * @a 1'b1 : pull down is enable
 * </pre>
 */
#define PIN_PULLDOWN_CTRL_PAD_MOSI2               PIN_PULLDOWN_CTRL_PAD_MOSI2_Msk

#define PIN_PULLDOWN_CTRL_PAD_MISO2_Pos           (6U)    ///< Poision of PIN_PULLDOWN_CTRL_PAD_MISO2
#define PIN_PULLDOWN_CTRL_PAD_MISO2_Msk           (0x1UL << PIN_PULLDOWN_CTRL_PAD_MISO2_Pos)    ///< Bitmask of PIN_PULLDOWN_CTRL_PAD_MISO2
/**
 * @def   PIN_PULLDOWN_CTRL_PAD_MISO2
 * @brief IO pin pull up/pull function disable control.
 * <pre>
 * @a 1'b0 : pull down is disable
 * @a 1'b1 : pull down is enable
 * </pre>
 */
#define PIN_PULLDOWN_CTRL_PAD_MISO2               PIN_PULLDOWN_CTRL_PAD_MISO2_Msk

#define PIN_PULLDOWN_CTRL_PAD_SSB2_Pos            (7U)    ///< Poision of PIN_PULLDOWN_CTRL_PAD_SSB2
#define PIN_PULLDOWN_CTRL_PAD_SSB2_Msk            (0x1UL << PIN_PULLDOWN_CTRL_PAD_SSB2_Pos)    ///< Bitmask of PIN_PULLDOWN_CTRL_PAD_SSB2
/**
 * @def   PIN_PULLDOWN_CTRL_PAD_SSB2
 * @brief IO pin pull up/pull function disable control.
 * <pre>
 * @a 1'b0 : pull down is disable
 * @a 1'b1 : pull down is enable
 * </pre>
 */
#define PIN_PULLDOWN_CTRL_PAD_SSB2                PIN_PULLDOWN_CTRL_PAD_SSB2_Msk

#define PIN_PULLDOWN_CTRL_PAD_SSB3_Pos            (8U)    ///< Poision of PIN_PULLDOWN_CTRL_PAD_SSB3
#define PIN_PULLDOWN_CTRL_PAD_SSB3_Msk            (0x1UL << PIN_PULLDOWN_CTRL_PAD_SSB3_Pos)    ///< Bitmask of PIN_PULLDOWN_CTRL_PAD_SSB3
/**
 * @def   PIN_PULLDOWN_CTRL_PAD_SSB3
 * @brief IO pin pull up/pull function disable control.
 * <pre>
 * @a 1'b0 : pull down is disable
 * @a 1'b1 : pull down is enable
 * </pre>
 */
#define PIN_PULLDOWN_CTRL_PAD_SSB3                PIN_PULLDOWN_CTRL_PAD_SSB3_Msk

#define PIN_PULLDOWN_CTRL_PAD_ID_Pos              (9U)    ///< Poision of PIN_PULLDOWN_CTRL_PAD_ID
#define PIN_PULLDOWN_CTRL_PAD_ID_Msk              (0x1UL << PIN_PULLDOWN_CTRL_PAD_ID_Pos)    ///< Bitmask of PIN_PULLDOWN_CTRL_PAD_ID
/**
 * @def   PIN_PULLDOWN_CTRL_PAD_ID
 * @brief IO pin pull up/pull function disable control.
 * <pre>
 * @a 1'b0 : pull down is disable
 * @a 1'b1 : pull down is enable
 * </pre>
 */
#define PIN_PULLDOWN_CTRL_PAD_ID                  PIN_PULLDOWN_CTRL_PAD_ID_Msk

#define PIN_PULLDOWN_CTRL_PAD_SCL1_Pos            (10U)    ///< Poision of PIN_PULLDOWN_CTRL_PAD_SCL1
#define PIN_PULLDOWN_CTRL_PAD_SCL1_Msk            (0x1UL << PIN_PULLDOWN_CTRL_PAD_SCL1_Pos)    ///< Bitmask of PIN_PULLDOWN_CTRL_PAD_SCL1
/**
 * @def   PIN_PULLDOWN_CTRL_PAD_SCL1
 * @brief IO pin pull up/pull function disable control.
 * <pre>
 * @a 1'b0 : pull down is disable
 * @a 1'b1 : pull down is enable
 * </pre>
 */
#define PIN_PULLDOWN_CTRL_PAD_SCL1                PIN_PULLDOWN_CTRL_PAD_SCL1_Msk

#define PIN_PULLDOWN_CTRL_PAD_SDA1_Pos            (11U)    ///< Poision of PIN_PULLDOWN_CTRL_PAD_SDA1
#define PIN_PULLDOWN_CTRL_PAD_SDA1_Msk            (0x1UL << PIN_PULLDOWN_CTRL_PAD_SDA1_Pos)    ///< Bitmask of PIN_PULLDOWN_CTRL_PAD_SDA1
/**
 * @def   PIN_PULLDOWN_CTRL_PAD_SDA1
 * @brief IO pin pull up/pull function disable control.
 * <pre>
 * @a 1'b0 : pull down is disable
 * @a 1'b1 : pull down is enable
 * </pre>
 */
#define PIN_PULLDOWN_CTRL_PAD_SDA1                PIN_PULLDOWN_CTRL_PAD_SDS1_Msk

#define PIN_PULLDOWN_CTRL_PAD_XVS_Pos             (12U)    ///< Poision of PIN_PULLDOWN_CTRL_PAD_XVS
#define PIN_PULLDOWN_CTRL_PAD_XVS_Msk             (0x1UL << PIN_PULLDOWN_CTRL_PAD_XVS_Pos)    ///< Bitmask of PIN_PULLDOWN_CTRL_PAD_XVS
/**
 * @def   PIN_PULLDOWN_CTRL_PAD_XVS
 * @brief IO pin pull up/pull function disable control.
 * <pre>
 * @a 1'b0 : pull down is disable
 * @a 1'b1 : pull down is enable
 * </pre>
 */
#define PIN_PULLDOWN_CTRL_PAD_XVS                 PIN_PULLDOWN_CTRL_PAD_XVS_Msk

#define PIN_PULLDOWN_CTRL_PAD_ECLK_Pos            (13U)    ///< Poision of PIN_PULLDOWN_CTRL_PAD_ECLK
#define PIN_PULLDOWN_CTRL_PAD_ECLK_Msk            (0x1UL << PIN_PULLDOWN_CTRL_PAD_ECLK_Pos)    ///< Bitmask of PIN_PULLDOWN_CTRL_PAD_ECLK
/**
 * @def   PIN_PULLDOWN_CTRL_PAD_ECLK
 * @brief IO pin pull up/pull function disable control.
 * <pre>
 * @a 1'b0 : pull down is disable
 * @a 1'b1 : pull down is enable
 * </pre>
 */
#define PIN_PULLDOWN_CTRL_PAD_ECLK                PIN_PULLDOWN_CTRL_PAD_ECLK_Msk

#define PIN_PULLDOWN_CTRL_PAD_INT_Pos             (14U)    ///< Poision of PIN_PULLDOWN_CTRL_PAD_INT
#define PIN_PULLDOWN_CTRL_PAD_INT_Msk             (0x1UL << PIN_PULLDOWN_CTRL_PAD_INT_Pos)    ///< Bitmask of PIN_PULLDOWN_CTRL_PAD_INT
/**
 * @def   PIN_PULLDOWN_CTRL_PAD_INT
 * @brief IO pin pull up/pull function disable control.
 * <pre>
 * @a 1'b0 : pull down is disable
 * @a 1'b1 : pull down is enable
 * </pre>
 */
#define PIN_PULLDOWN_CTRL_PAD_INT                 PIN_PULLDOWN_CTRL_PAD_INT_Msk

#define PIN_PULLDOWN_CTRL_PAD_GPIO0_Pos           (15U)    ///< Poision of PIN_PULLDOWN_CTRL_PAD_GPIO0
#define PIN_PULLDOWN_CTRL_PAD_GPIO0_Msk           (0x1UL << PIN_PULLDOWN_CTRL_PAD_GPIO0_Pos)    ///< Bitmask of PIN_PULLDOWN_CTRL_PAD_GPIO0
/**
 * @def   PIN_PULLDOWN_CTRL_PAD_GPIO0
 * @brief IO pin pull up/pull function disable control.
 * <pre>
 * @a 1'b0 : pull down is disable
 * @a 1'b1 : pull down is enable
 * </pre>
 */
#define PIN_PULLDOWN_CTRL_PAD_GPIO0               PIN_PULLDOWN_CTRL_PAD_GPIO0_Msk

#define PIN_PULLDOWN_CTRL_PAD_GPIO1_Pos           (16U)    ///< Poision of PIN_PULLDOWN_CTRL_PAD_GPIO1
#define PIN_PULLDOWN_CTRL_PAD_GPIO1_Msk           (0x1UL << PIN_PULLDOWN_CTRL_PAD_GPIO1_Pos)    ///< Bitmask of PIN_PULLDOWN_CTRL_PAD_GPIO1
/**
 * @def   PIN_PULLDOWN_CTRL_PAD_GPIO1
 * @brief IO pin pull up/pull function disable control.
 * <pre>
 * @a 1'b0 : pull down is disable
 * @a 1'b1 : pull down is enable
 * </pre>
 */
#define PIN_PULLDOWN_CTRL_PAD_GPIO1               PIN_PULLDOWN_CTRL_PAD_GPIO1_Msk

#define PIN_PULLDOWN_CTRL_PAD_HLXBO_Pos           (17U)    ///< Poision of PIN_PULLDOWN_CTRL_PAD_HLXBO
#define PIN_PULLDOWN_CTRL_PAD_HLXBO_Msk           (0x1UL << PIN_PULLDOWN_CTRL_PAD_HLXBO_Pos)    ///< Bitmask of PIN_PULLDOWN_CTRL_PAD_HLXBO
/**
 * @def   PIN_PULLDOWN_CTRL_PAD_HLXBO
 * @brief IO pin pull up/pull function disable control.
 * <pre>
 * @a 1'b0 : pull down is disable
 * @a 1'b1 : pull down is enable
 * </pre>
 */
#define PIN_PULLDOWN_CTRL_PAD_HLXBO               PIN_PULLDOWN_CTRL_PAD_HLXBO_Msk

#define PIN_PULLDOWN_CTRL_PAD_HLYBO_Pos           (18U)    ///< Poision of PIN_PULLDOWN_CTRL_PAD_HLYBO
#define PIN_PULLDOWN_CTRL_PAD_HLYBO_Msk           (0x1UL << PIN_PULLDOWN_CTRL_PAD_HLYBO_Pos)    ///< Bitmask of PIN_PULLDOWN_CTRL_PAD_HLYBO
/**
 * @def   PIN_PULLDOWN_CTRL_PAD_HLYBO
 * @brief IO pin pull up/pull function disable control.
 * <pre>
 * @a 1'b0 : pull down is disable
 * @a 1'b1 : pull down is enable
 * </pre>
 */
#define PIN_PULLDOWN_CTRL_PAD_HLYBO               PIN_PULLDOWN_CTRL_PAD_HLYBO_Msk

#define PIN_DS_CTRL_PAD_SCLK1_Pos                 (0U)    ///< Poision of PIN_DS_CTRL_PAD_SCLK1
#define PIN_DS_CTRL_PAD_SCLK1_Msk                 (0x1UL << PIN_DS_CTRL_PAD_SCLK1_Pos)    ///< Bitmask of PIN_DS_CTRL_PAD_SCLK1
/**
 * @def   PIN_DS_CTRL_PAD_SCLK1
 * @brief I/O pin driving strength control.
 * <pre>
 * @a 1'b0 : High driving strength
 * @a 1'b1 : Low driving strength
 * </pre>
 */
#define PIN_DS_CTRL_PAD_SCLK1                     PIN_DS_CTRL_PAD_SCLK1_Msk

#define PIN_DS_CTRL_PAD_MOSI1_Pos                 (1U)    ///< Poision of PIN_DS_CTRL_PAD_MOSI1
#define PIN_DS_CTRL_PAD_MOSI1_Msk                 (0x1UL << PIN_DS_CTRL_PAD_MOSI1_Pos)    ///< Bitmask of PIN_DS_CTRL_PAD_MOSI1
/**
 * @def   PIN_DS_CTRL_PAD_MOSI1
 * @brief I/O pin driving strength control.
 * <pre>
 * @a 1'b0 : High driving strength
 * @a 1'b1 : Low driving strength
 * </pre>
 */
#define PIN_DS_CTRL_PAD_MOSI1                     PIN_DS_CTRL_PAD_MOSI1_Msk

#define PIN_DS_CTRL_PAD_MISO1_Pos                 (2U)    ///< Poision of PIN_DS_CTRL_PAD_MISO1
#define PIN_DS_CTRL_PAD_MISO1_Msk                 (0x1UL << PIN_DS_CTRL_PAD_MISO1_Pos)    ///< Bitmask of PIN_DS_CTRL_PAD_MISO1
/**
 * @def   PIN_DS_CTRL_PAD_MISO1
 * @brief I/O pin driving strength control.
 * <pre>
 * @a 1'b0 : High driving strength
 * @a 1'b1 : Low driving strength
 * </pre>
 */
#define PIN_DS_CTRL_PAD_MISO1                     PIN_DS_CTRL_PAD_MISO1_Msk

#define PIN_DS_CTRL_PAD_SSB1_Pos                  (3U)    ///< Poision of PIN_DS_CTRL_PAD_SSB1
#define PIN_DS_CTRL_PAD_SSB1_Msk                  (0x1UL << PIN_DS_CTRL_PAD_SSB1_Pos)    ///< Bitmask of PIN_DS_CTRL_PAD_SSB1
/**
 * @def   PIN_DS_CTRL_PAD_SSB1
 * @brief I/O pin driving strength control.
 * <pre>
 * @a 1'b0 : High driving strength
 * @a 1'b1 : Low driving strength
 * </pre>
 */
#define PIN_DS_CTRL_PAD_SSB1                      PIN_DS_CTRL_PAD_SSB1_Msk

#define PIN_DS_CTRL_PAD_SCLK2_Pos                 (4U)    ///< Poision of PIN_DS_CTRL_PAD_SCLK2
#define PIN_DS_CTRL_PAD_SCLK2_Msk                 (0x1UL << PIN_DS_CTRL_PAD_SCLK2_Pos)    ///< Bitmask of PIN_DS_CTRL_PAD_SCLK2
/**
 * @def   PIN_DS_CTRL_PAD_SCLK2
 * @brief I/O pin driving strength control.
 * <pre>
 * @a 1'b0 : High driving strength
 * @a 1'b1 : Low driving strength
 * </pre>
 */
#define PIN_DS_CTRL_PAD_SCLK2                     PIN_DS_CTRL_PAD_SCLK2_Msk

#define PIN_DS_CTRL_PAD_MOSI2_Pos                 (5U)    ///< Poision of PIN_DS_CTRL_PAD_MOSI2
#define PIN_DS_CTRL_PAD_MOSI2_Msk                 (0x1UL << PIN_DS_CTRL_PAD_MOSI2_Pos)    ///< Bitmask of PIN_DS_CTRL_PAD_MOSI2
/**
 * @def   PIN_DS_CTRL_PAD_MOSI2
 * @brief I/O pin driving strength control.
 * <pre>
 * @a 1'b0 : High driving strength
 * @a 1'b1 : Low driving strength
 * </pre>
 */
#define PIN_DS_CTRL_PAD_MOSI2                     PIN_DS_CTRL_PAD_MOSI2_Msk

#define PIN_DS_CTRL_PAD_MISO2_Pos                 (6U)    ///< Poision of PIN_DS_CTRL_PAD_MISO2
#define PIN_DS_CTRL_PAD_MISO2_Msk                 (0x1UL << PIN_DS_CTRL_PAD_MISO2_Pos)    ///< Bitmask of PIN_DS_CTRL_PAD_MISO2
/**
 * @def   PIN_DS_CTRL_PAD_MISO2
 * @brief I/O pin driving strength control.
 * <pre>
 * @a 1'b0 : High driving strength
 * @a 1'b1 : Low driving strength
 * </pre>
 */
#define PIN_DS_CTRL_PAD_MISO2                     PIN_DS_CTRL_PAD_MISO2_Msk

#define PIN_DS_CTRL_PAD_SSB2_Pos                  (7U)    ///< Poision of PIN_DS_CTRL_PAD_SSB2
#define PIN_DS_CTRL_PAD_SSB2_Msk                  (0x1UL << PIN_DS_CTRL_PAD_SSB2_Pos)    ///< Bitmask of PIN_DS_CTRL_PAD_SSB2
/**
 * @def   PIN_DS_CTRL_PAD_SSB2
 * @brief I/O pin driving strength control.
 * <pre>
 * @a 1'b0 : High driving strength
 * @a 1'b1 : Low driving strength
 * </pre>
 */
#define PIN_DS_CTRL_PAD_SSB2                      PIN_DS_CTRL_PAD_SSB2_Msk

#define PIN_DS_CTRL_PAD_SSB3_Pos                  (8U)    ///< Poision of PIN_DS_CTRL_PAD_SSB3
#define PIN_DS_CTRL_PAD_SSB3_Msk                  (0x1UL << PIN_DS_CTRL_PAD_SSB3_Pos)    ///< Bitmask of PIN_DS_CTRL_PAD_SSB3
/**
 * @def   PIN_DS_CTRL_PAD_SSB3
 * @brief I/O pin driving strength control.
 * <pre>
 * @a 1'b0 : High driving strength
 * @a 1'b1 : Low driving strength
 * </pre>
 */
#define PIN_DS_CTRL_PAD_SSB3                      PIN_DS_CTRL_PAD_SSB3_Msk

#define PIN_DS_CTRL_PAD_ID_Pos                    (9U)    ///< Poision of PIN_DS_CTRL_PAD_ID
#define PIN_DS_CTRL_PAD_ID_Msk                    (0x1UL << PIN_DS_CTRL_PAD_ID_Pos)    ///< Bitmask of PIN_DS_CTRL_PAD_ID
/**
 * @def   PIN_DS_CTRL_PAD_ID
 * @brief I/O pin driving strength control.
 * <pre>
 * @a 1'b0 : High driving strength
 * @a 1'b1 : Low driving strength
 * </pre>
 */
#define PIN_DS_CTRL_PAD_ID                        PIN_DS_CTRL_PAD_ID_Msk

#define PIN_DS_CTRL_PAD_SCL1_Pos                  (10U)    ///< Poision of PIN_DS_CTRL_PAD_SCL1
#define PIN_DS_CTRL_PAD_SCL1_Msk                  (0x1UL << PIN_DS_CTRL_PAD_SCL1_Pos)    ///< Bitmask of PIN_DS_CTRL_PAD_SCL1
/**
 * @def   PIN_DS_CTRL_PAD_SCL1
 * @brief I/O pin driving strength control.
 * <pre>
 * @a 1'b0 : High driving strength
 * @a 1'b1 : Low driving strength
 * </pre>
 */
#define PIN_DS_CTRL_PAD_SCL1                      PIN_DS_CTRL_PAD_SCL1_Msk

#define PIN_DS_CTRL_PAD_SDA1_Pos                  (11U)    ///< Poision of PIN_DS_CTRL_PAD_SDA1
#define PIN_DS_CTRL_PAD_SDA1_Msk                  (0x1UL << PIN_DS_CTRL_PAD_SDA1_Pos)    ///< Bitmask of PIN_DS_CTRL_PAD_SDA1
/**
 * @def   PIN_DS_CTRL_PAD_SDA1
 * @brief I/O pin driving strength control.
 * <pre>
 * @a 1'b0 : High driving strength
 * @a 1'b1 : Low driving strength
 * </pre>
 */
#define PIN_DS_CTRL_PAD_SDA1                      PIN_DS_CTRL_PAD_SDS1_Msk

#define PIN_DS_CTRL_PAD_XVS_Pos                   (12U)    ///< Poision of PIN_DS_CTRL_PAD_XVS
#define PIN_DS_CTRL_PAD_XVS_Msk                   (0x1UL << PIN_DS_CTRL_PAD_XVS_Pos)    ///< Bitmask of PIN_DS_CTRL_PAD_XVS
/**
 * @def   PIN_DS_CTRL_PAD_XVS
 * @brief I/O pin driving strength control.
 * <pre>
 * @a 1'b0 : High driving strength
 * @a 1'b1 : Low driving strength
 * </pre>
 */
#define PIN_DS_CTRL_PAD_XVS                       PIN_DS_CTRL_PAD_XVS_Msk

#define PIN_DS_CTRL_PAD_ECLK_Pos                  (13U)    ///< Poision of PIN_DS_CTRL_PAD_ECLK
#define PIN_DS_CTRL_PAD_ECLK_Msk                  (0x1UL << PIN_DS_CTRL_PAD_ECLK_Pos)    ///< Bitmask of PIN_DS_CTRL_PAD_ECLK
/**
 * @def   PIN_DS_CTRL_PAD_ECLK
 * @brief I/O pin driving strength control.
 * <pre>
 * @a 1'b0 : High driving strength
 * @a 1'b1 : Low driving strength
 * </pre>
 */
#define PIN_DS_CTRL_PAD_ECLK                      PIN_DS_CTRL_PAD_ECLK_Msk

#define PIN_DS_CTRL_PAD_INT_Pos                   (14U)    ///< Poision of PIN_DS_CTRL_PAD_INT
#define PIN_DS_CTRL_PAD_INT_Msk                   (0x1UL << PIN_DS_CTRL_PAD_INT_Pos)    ///< Bitmask of PIN_DS_CTRL_PAD_INT
/**
 * @def   PIN_DS_CTRL_PAD_INT
 * @brief I/O pin driving strength control.
 * <pre>
 * @a 1'b0 : High driving strength
 * @a 1'b1 : Low driving strength
 * </pre>
 */
#define PIN_DS_CTRL_PAD_INT                       PIN_DS_CTRL_PAD_INT_Msk

#define PIN_DS_CTRL_PAD_GPIO0_Pos                 (15U)    ///< Poision of PIN_DS_CTRL_PAD_GPIO0
#define PIN_DS_CTRL_PAD_GPIO0_Msk                 (0x1UL << PIN_DS_CTRL_PAD_GPIO0_Pos)    ///< Bitmask of PIN_DS_CTRL_PAD_GPIO0
/**
 * @def   PIN_DS_CTRL_PAD_GPIO0
 * @brief I/O pin driving strength control.
 * <pre>
 * @a 1'b0 : High driving strength
 * @a 1'b1 : Low driving strength
 * </pre>
 */
#define PIN_DS_CTRL_PAD_GPIO0                     PIN_DS_CTRL_PAD_GPIO0_Msk

#define PIN_DS_CTRL_PAD_GPIO1_Pos                 (16U)    ///< Poision of PIN_DS_CTRL_PAD_GPIO1
#define PIN_DS_CTRL_PAD_GPIO1_Msk                 (0x1UL << PIN_DS_CTRL_PAD_GPIO1_Pos)    ///< Bitmask of PIN_DS_CTRL_PAD_GPIO1
/**
 * @def   PIN_DS_CTRL_PAD_GPIO1
 * @brief I/O pin driving strength control.
 * <pre>
 * @a 1'b0 : High driving strength
 * @a 1'b1 : Low driving strength
 * </pre>
 */
#define PIN_DS_CTRL_PAD_GPIO1                     PIN_DS_CTRL_PAD_GPIO1_Msk

#define PIN_DS_CTRL_PAD_HLXBO_Pos                 (17U)    ///< Poision of PIN_DS_CTRL_PAD_HLXBO
#define PIN_DS_CTRL_PAD_HLXBO_Msk                 (0x1UL << PIN_DS_CTRL_PAD_HLXBO_Pos)    ///< Bitmask of PIN_DS_CTRL_PAD_HLXBO
/**
 * @def   PIN_DS_CTRL_PAD_HLXBO
 * @brief I/O pin driving strength control.
 * <pre>
 * @a 1'b0 : High driving strength
 * @a 1'b1 : Low driving strength
 * </pre>
 */
#define PIN_DS_CTRL_PAD_HLXBO                     PIN_DS_CTRL_PAD_HLXBO_Msk

#define PIN_DS_CTRL_PAD_HLYBO_Pos                 (18U)    ///< Poision of PIN_DS_CTRL_PAD_HLYBO
#define PIN_DS_CTRL_PAD_HLYBO_Msk                 (0x1UL << PIN_DS_CTRL_PAD_HLYBO_Pos)    ///< Bitmask of PIN_DS_CTRL_PAD_HLYBO
/**
 * @def   PIN_DS_CTRL_PAD_HLYBO
 * @brief I/O pin driving strength control.
 * <pre>
 * @a 1'b0 : High driving strength
 * @a 1'b1 : Low driving strength
 * </pre>
 */
#define PIN_DS_CTRL_PAD_HLYBO                     PIN_DS_CTRL_PAD_HLYBO_Msk

#define PIN_SL_CTRL_PAD_SCLK1_Pos                 (0U)    ///< Poision of PIN_SL_CTRL_PAD_SCLK1
#define PIN_SL_CTRL_PAD_SCLK1_Msk                 (0x1UL << PIN_SL_CTRL_PAD_SCLK1_Pos)    ///< Bitmask of PIN_SL_CTRL_PAD_SCLK1
/**
 * @def   PIN_SL_CTRL_PAD_SCLK1
 * @brief Ouptut slew rate control for IO pins.
 * <pre>
 * @a 1'b0 : Fast slew rate
 * @a 1'b1 : Slow slew rate
 * </pre>
 */
#define PIN_SL_CTRL_PAD_SCLK1                     PIN_SL_CTRL_PAD_SCLK1_Msk

#define PIN_SL_CTRL_PAD_MOSI1_Pos                 (1U)    ///< Poision of PIN_SL_CTRL_PAD_MOSI1
#define PIN_SL_CTRL_PAD_MOSI1_Msk                 (0x1UL << PIN_SL_CTRL_PAD_MOSI1_Pos)    ///< Bitmask of PIN_SL_CTRL_PAD_MOSI1
/**
 * @def   PIN_SL_CTRL_PAD_MOSI1
 * @brief Ouptut slew rate control for IO pins.
 * <pre>
 * @a 1'b0 : Fast slew rate
 * @a 1'b1 : Slow slew rate
 * </pre>
 */
#define PIN_SL_CTRL_PAD_MOSI1                     PIN_SL_CTRL_PAD_MOSI1_Msk

#define PIN_SL_CTRL_PAD_MISO1_Pos                 (2U)    ///< Poision of PIN_SL_CTRL_PAD_MISO1
#define PIN_SL_CTRL_PAD_MISO1_Msk                 (0x1UL << PIN_SL_CTRL_PAD_MISO1_Pos)    ///< Bitmask of PIN_SL_CTRL_PAD_MISO1
/**
 * @def   PIN_SL_CTRL_PAD_MISO1
 * @brief Ouptut slew rate control for IO pins.
 * <pre>
 * @a 1'b0 : Fast slew rate
 * @a 1'b1 : Slow slew rate
 * </pre>
 */
#define PIN_SL_CTRL_PAD_MISO1                     PIN_SL_CTRL_PAD_MISO1_Msk

#define PIN_SL_CTRL_PAD_SSB1_Pos                  (3U)    ///< Poision of PIN_SL_CTRL_PAD_SSB1
#define PIN_SL_CTRL_PAD_SSB1_Msk                  (0x1UL << PIN_SL_CTRL_PAD_SSB1_Pos)    ///< Bitmask of PIN_SL_CTRL_PAD_SSB1
/**
 * @def   PIN_SL_CTRL_PAD_SSB1
 * @brief Ouptut slew rate control for IO pins.
 * <pre>
 * @a 1'b0 : Fast slew rate
 * @a 1'b1 : Slow slew rate
 * </pre>
 */
#define PIN_SL_CTRL_PAD_SSB1                      PIN_SL_CTRL_PAD_SSB1_Msk

#define PIN_SL_CTRL_PAD_SCLK2_Pos                 (4U)    ///< Poision of PIN_SL_CTRL_PAD_SCLK2
#define PIN_SL_CTRL_PAD_SCLK2_Msk                 (0x1UL << PIN_SL_CTRL_PAD_SCLK2_Pos)    ///< Bitmask of PIN_SL_CTRL_PAD_SCLK2
/**
 * @def   PIN_SL_CTRL_PAD_SCLK2
 * @brief Ouptut slew rate control for IO pins.
 * <pre>
 * @a 1'b0 : Fast slew rate
 * @a 1'b1 : Slow slew rate
 * </pre>
 */
#define PIN_SL_CTRL_PAD_SCLK2                     PIN_SL_CTRL_PAD_SCLK2_Msk

#define PIN_SL_CTRL_PAD_MOSI2_Pos                 (5U)    ///< Poision of PIN_SL_CTRL_PAD_MOSI2
#define PIN_SL_CTRL_PAD_MOSI2_Msk                 (0x1UL << PIN_SL_CTRL_PAD_MOSI2_Pos)    ///< Bitmask of PIN_SL_CTRL_PAD_MOSI2
/**
 * @def   PIN_SL_CTRL_PAD_MOSI2
 * @brief Ouptut slew rate control for IO pins.
 * <pre>
 * @a 1'b0 : Fast slew rate
 * @a 1'b1 : Slow slew rate
 * </pre>
 */
#define PIN_SL_CTRL_PAD_MOSI2                     PIN_SL_CTRL_PAD_MOSI2_Msk

#define PIN_SL_CTRL_PAD_MISO2_Pos                 (6U)    ///< Poision of PIN_SL_CTRL_PAD_MISO2
#define PIN_SL_CTRL_PAD_MISO2_Msk                 (0x1UL << PIN_SL_CTRL_PAD_MISO2_Pos)    ///< Bitmask of PIN_SL_CTRL_PAD_MISO2
/**
 * @def   PIN_SL_CTRL_PAD_MISO2
 * @brief Ouptut slew rate control for IO pins.
 * <pre>
 * @a 1'b0 : Fast slew rate
 * @a 1'b1 : Slow slew rate
 * </pre>
 */
#define PIN_SL_CTRL_PAD_MISO2                     PIN_SL_CTRL_PAD_MISO2_Msk

#define PIN_SL_CTRL_PAD_SSB2_Pos                  (7U)    ///< Poision of PIN_SL_CTRL_PAD_SSB2
#define PIN_SL_CTRL_PAD_SSB2_Msk                  (0x1UL << PIN_SL_CTRL_PAD_SSB2_Pos)    ///< Bitmask of PIN_SL_CTRL_PAD_SSB2
/**
 * @def   PIN_SL_CTRL_PAD_SSB2
 * @brief Ouptut slew rate control for IO pins.
 * <pre>
 * @a 1'b0 : Fast slew rate
 * @a 1'b1 : Slow slew rate
 * </pre>
 */
#define PIN_SL_CTRL_PAD_SSB2                      PIN_SL_CTRL_PAD_SSB2_Msk

#define PIN_SL_CTRL_PAD_SSB3_Pos                  (8U)    ///< Poision of PIN_SL_CTRL_PAD_SSB3
#define PIN_SL_CTRL_PAD_SSB3_Msk                  (0x1UL << PIN_SL_CTRL_PAD_SSB3_Pos)    ///< Bitmask of PIN_SL_CTRL_PAD_SSB3
/**
 * @def   PIN_SL_CTRL_PAD_SSB3
 * @brief Ouptut slew rate control for IO pins.
 * <pre>
 * @a 1'b0 : Fast slew rate
 * @a 1'b1 : Slow slew rate
 * </pre>
 */
#define PIN_SL_CTRL_PAD_SSB3                      PIN_SL_CTRL_PAD_SSB3_Msk

#define PIN_SL_CTRL_PAD_ID_Pos                    (9U)    ///< Poision of PIN_SL_CTRL_PAD_ID
#define PIN_SL_CTRL_PAD_ID_Msk                    (0x1UL << PIN_SL_CTRL_PAD_ID_Pos)    ///< Bitmask of PIN_SL_CTRL_PAD_ID
/**
 * @def   PIN_SL_CTRL_PAD_ID
 * @brief Ouptut slew rate control for IO pins.
 * <pre>
 * @a 1'b0 : Fast slew rate
 * @a 1'b1 : Slow slew rate
 * </pre>
 */
#define PIN_SL_CTRL_PAD_ID                        PIN_SL_CTRL_PAD_ID_Msk

#define PIN_SL_CTRL_PAD_SCL1_Pos                  (10U)    ///< Poision of PIN_SL_CTRL_PAD_SCL1
#define PIN_SL_CTRL_PAD_SCL1_Msk                  (0x1UL << PIN_SL_CTRL_PAD_SCL1_Pos)    ///< Bitmask of PIN_SL_CTRL_PAD_SCL1
/**
 * @def   PIN_SL_CTRL_PAD_SCL1
 * @brief Ouptut slew rate control for IO pins.
 * <pre>
 * @a 1'b0 : Fast slew rate
 * @a 1'b1 : Slow slew rate
 * </pre>
 */
#define PIN_SL_CTRL_PAD_SCL1                      PIN_SL_CTRL_PAD_SCL1_Msk

#define PIN_SL_CTRL_PAD_SDA1_Pos                  (11U)    ///< Poision of PIN_SL_CTRL_PAD_SDA1
#define PIN_SL_CTRL_PAD_SDA1_Msk                  (0x1UL << PIN_SL_CTRL_PAD_SDA1_Pos)    ///< Bitmask of PIN_SL_CTRL_PAD_SDA1
/**
 * @def   PIN_SL_CTRL_PAD_SDA1
 * @brief Ouptut slew rate control for IO pins.
 * <pre>
 * @a 1'b0 : Fast slew rate
 * @a 1'b1 : Slow slew rate
 * </pre>
 */
#define PIN_SL_CTRL_PAD_SDA1                      PIN_SL_CTRL_PAD_SDS1_Msk

#define PIN_SL_CTRL_PAD_XVS_Pos                   (12U)    ///< Poision of PIN_SL_CTRL_PAD_XVS
#define PIN_SL_CTRL_PAD_XVS_Msk                   (0x1UL << PIN_SL_CTRL_PAD_XVS_Pos)    ///< Bitmask of PIN_SL_CTRL_PAD_XVS
/**
 * @def   PIN_SL_CTRL_PAD_XVS
 * @brief Ouptut slew rate control for IO pins.
 * <pre>
 * @a 1'b0 : Fast slew rate
 * @a 1'b1 : Slow slew rate
 * </pre>
 */
#define PIN_SL_CTRL_PAD_XVS                       PIN_SL_CTRL_PAD_XVS_Msk

#define PIN_SL_CTRL_PAD_ECLK_Pos                  (13U)    ///< Poision of PIN_SL_CTRL_PAD_ECLK
#define PIN_SL_CTRL_PAD_ECLK_Msk                  (0x1UL << PIN_SL_CTRL_PAD_ECLK_Pos)    ///< Bitmask of PIN_SL_CTRL_PAD_ECLK
/**
 * @def   PIN_SL_CTRL_PAD_ECLK
 * @brief Ouptut slew rate control for IO pins.
 * <pre>
 * @a 1'b0 : Fast slew rate
 * @a 1'b1 : Slow slew rate
 * </pre>
 */
#define PIN_SL_CTRL_PAD_ECLK                      PIN_SL_CTRL_PAD_ECLK_Msk

#define PIN_SL_CTRL_PAD_INT_Pos                   (14U)    ///< Poision of PIN_SL_CTRL_PAD_INT
#define PIN_SL_CTRL_PAD_INT_Msk                   (0x1UL << PIN_SL_CTRL_PAD_INT_Pos)    ///< Bitmask of PIN_SL_CTRL_PAD_INT
/**
 * @def   PIN_SL_CTRL_PAD_INT
 * @brief Ouptut slew rate control for IO pins.
 * <pre>
 * @a 1'b0 : Fast slew rate
 * @a 1'b1 : Slow slew rate
 * </pre>
 */
#define PIN_SL_CTRL_PAD_INT                       PIN_SL_CTRL_PAD_INT_Msk

#define PIN_SL_CTRL_PAD_GPIO0_Pos                 (15U)    ///< Poision of PIN_SL_CTRL_PAD_GPIO0
#define PIN_SL_CTRL_PAD_GPIO0_Msk                 (0x1UL << PIN_SL_CTRL_PAD_GPIO0_Pos)    ///< Bitmask of PIN_SL_CTRL_PAD_GPIO0
/**
 * @def   PIN_SL_CTRL_PAD_GPIO0
 * @brief Ouptut slew rate control for IO pins.
 * <pre>
 * @a 1'b0 : Fast slew rate
 * @a 1'b1 : Slow slew rate
 * </pre>
 */
#define PIN_SL_CTRL_PAD_GPIO0                     PIN_SL_CTRL_PAD_GPIO0_Msk

#define PIN_SL_CTRL_PAD_GPIO1_Pos                 (16U)    ///< Poision of PIN_SL_CTRL_PAD_GPIO1
#define PIN_SL_CTRL_PAD_GPIO1_Msk                 (0x1UL << PIN_SL_CTRL_PAD_GPIO1_Pos)    ///< Bitmask of PIN_SL_CTRL_PAD_GPIO1
/**
 * @def   PIN_SL_CTRL_PAD_GPIO1
 * @brief Ouptut slew rate control for IO pins.
 * <pre>
 * @a 1'b0 : Fast slew rate
 * @a 1'b1 : Slow slew rate
 * </pre>
 */
#define PIN_SL_CTRL_PAD_GPIO1                     PIN_SL_CTRL_PAD_GPIO1_Msk

#define PIN_SL_CTRL_PAD_HLXBO_Pos                 (17U)    ///< Poision of PIN_SL_CTRL_PAD_HLXBO
#define PIN_SL_CTRL_PAD_HLXBO_Msk                 (0x1UL << PIN_SL_CTRL_PAD_HLXBO_Pos)    ///< Bitmask of PIN_SL_CTRL_PAD_HLXBO
/**
 * @def   PIN_SL_CTRL_PAD_HLXBO
 * @brief Ouptut slew rate control for IO pins.
 * <pre>
 * @a 1'b0 : Fast slew rate
 * @a 1'b1 : Slow slew rate
 * </pre>
 */
#define PIN_SL_CTRL_PAD_HLXBO                     PIN_SL_CTRL_PAD_HLXBO_Msk

#define PIN_SL_CTRL_PAD_HLYBO_Pos                 (18U)    ///< Poision of PIN_SL_CTRL_PAD_HLYBO
#define PIN_SL_CTRL_PAD_HLYBO_Msk                 (0x1UL << PIN_SL_CTRL_PAD_HLYBO_Pos)    ///< Bitmask of PIN_SL_CTRL_PAD_HLYBO
/**
 * @def   PIN_SL_CTRL_PAD_HLYBO
 * @brief Ouptut slew rate control for IO pins.
 * <pre>
 * @a 1'b0 : Fast slew rate
 * @a 1'b1 : Slow slew rate
 * </pre>
 */
#define PIN_SL_CTRL_PAD_HLYBO                     PIN_SL_CTRL_PAD_HLYBO_Msk

/** @} IO_CFG_BITMAP*/
/** @} IO_CFG */


/**
 * @defgroup GPIO_Bitmap GPIO Bitmap
 * @ingroup  Peripheral_Registers_Bits_Definition
 * @brief    Bitmap of GPIO registers
 * @{
 */

#define GPIO_DATA_Pos         (0U)    ///< Position of GPIO_DATA
#define GPIO_DATA_Msk         (0xFFFFFFFFUL << GPIO_DATA_Pos)    ///< Bitmask of GPIO_DATA
/**
 * @def   GPIO_DATA
 * @brief Each bit driving the output data of corresponding gpio_out in software mode
 */
#define GPIO_DATA             GPIO_DATA_Msk

#define GPIO_DIR_Pos          (0U)    ///< Position of GPIO_DIR
#define GPIO_DIR_Msk          (0xFFFFFFFFUL << GPIO_DIR_Pos)    ///< Bitmask of GPIO_DIR
/**
 * @def   GPIO_DIR
 * @brief Each bit mapping to the gpio_en_n and control the direction of corresponding gpio_xp in software
 * <pre>
 * @a 1'b0 : for input from gpio_in,
 * @a 1'b1 : for output to gpio_out
 * </pre>
 */
#define GPIO_DIR              GPIO_DIR_Msk

#define GPIO_CTRL_Pos         (0U)    ///< Position of GPIO_CTRL
#define GPIO_CTRL_Msk         (0xFFFFFFFFUL << GPIO_CTRL_Pos)   ///< Bitmask of GPIO_CTRL
/**
 * @def   GPIO_CTRL
 * @brief Reserved
 */
#define GPIO_CTRL             GPIO_CTRL_Msk

#define GPIO_EXT_Pos          (0U)    ///< Position of GPIO_EXT
#define GPIO_EXT_Msk          (0xFFFFFFFFUL << GPIO_EXT_Pos)    ///< Bitmask of GPIO_EXT
/**
 * @def   GPIO_EXT
 * @brief For each bit, the value is the corresponding pin of gpio_in in input direction
 */
#define GPIO_EXT              GPIO_EXT_Msk

#define GPIO_IEN_Pos          (0U)    ///< Position of GPIO_IEN
#define GPIO_IEN_Msk          (0xFFFFFFFFUL << GPIO_IEN_Pos)    ///< Bitmask of GPIO_IEN
/**
 * @def   GPIO_IEN
 * @brief Disable or enable interrupt event
 * <pre>
 * @a 1'b0 : Disable the interrupt event on the corresponding pin
 * @a 1'b1 : Enable the corresponding pins trigger interrupt.
 * </pre>
 */
#define GPIO_IEN              GPIO_IEN_Msk

#define GPIO_IS_Pos           (0U)    ///< Position of GPIO_IS
#define GPIO_IS_Msk           (0xFFFFFFFFUL << GPIO_IS_Pos)   ///< Bitmask of GPIO_IS
/**
 * @def   GPIO_IS
 * @brief Interrupt triggered configuration
 * <pre>
 * @a 1'b0 : Edge-detecting
 * @a 1'b1 : Level-sensitive
 * </pre>
 */
#define GPIO_IS               GPIO_IS_Msk

#define GPIO_IBE_Pos          (0U)    ///< Position of GPIO_IBE
#define GPIO_IBE_Msk          (0xFFFFFFFFUL << GPIO_IBE_Pos)    ///< Bitmask of GPIO_IBE
/**
 * @def   GPIO_IBE
 * @brief Interrupt triggered configuration
 * <pre>
 * @a 1'b0 : Single edge-sensitive (either falling edge or rising edge), decided by the bit of gpio_iev
 * @a 1'b1 : Both edges on corresponding pin trigger an interrupt
 * </pre>
 */
#define GPIO_IBE              GPIO_IBE_Msk

#define GPIO_IEV_Pos          (0U)    ///< Position of GPIO_IEV
#define GPIO_IEV_Msk          (0xFFFFFFFFUL << GPIO_IEV_Pos)    ///< Bitmask of GPIO_IEV
/**
 * @def   GPIO_IEV
 * @brief Interrupt triggered configuration
 * <pre>
 * @a 1'b0 : Interrupt is triggered in falling edge of corresponding pins
 * @a 1'b1 : Interrupt is triggered in rising edge of corresponding pins
 * </pre>
 */
#define GPIO_IEV              GPIO_IEV_Msk

#define GPIO_RIS_Pos          (0U)    ///< Position of GPIO_RIS
#define GPIO_RIS_Msk          (0xFFFFFFFFUL << GPIO_RIS_Pos)    ///< Bitmask of GPIO_RIS
/**
 * @def   GPIO_RIS
 * @brief Raw Interrupt status register before masked
 * <pre>
 * @a 1'b0 : No raw Interrupt
 * @a 1'b1 : Raw Interrupt
 * </pre>
 */
#define GPIO_RIS              GPIO_RIS_Msk

#define GPIO_IM_Pos           (0U)    ///< Position of GPIO_IM
#define GPIO_IM_Msk           (0xFFFFFFFFUL << GPIO_IM_Pos)   ///< Bitmask of GPIO_IM
/**
 * @def   GPIO_IM
 * @brief Interrupt triggered configuration
 * <pre>
 * @a 1'b0 : The interrupt on the corresponding gpio_ext bit is unmasked
 * @a 1'b1 : The interrupt on the corresponding gpio_ext bit is masked
 * </pre>
 */
#define GPIO_IM               GPIO_IM_Msk

#define GPIO_MIS_Pos          (0U)    ///< Position of GPIO_MIS
#define GPIO_MIS_Msk          (0xFFFFFFFFUL << GPIO_MIS_Pos)    ///< Bitmask of GPIO_MIS
/**
 * @def   GPIO_MIS
 * @brief The masked interrupt status on the corresponding gpio_ext bit
 */
#define GPIO_MIS              GPIO_MIS_Msk

#define GPIO_IC_Pos           (0U)    ///< Position of GPIO_IC
#define GPIO_IC_Msk           (0xFFFFFFFFUL << GPIO_IC_Pos)   ///< Bitmask of GPIO_IC
/**
 * @def   GPIO_IC
 * @brief Interrupt triggered configuration
 * <pre>
 * @a 1'b0 : No effects on the corresponding interrupt
 * @a 1'b1 : Clear the edge-sensitive interrupt status on the corresponding pin
 * </pre>
 */
#define GPIO_IC               GPIO_IC_Msk

#define GPIO_DB_Pos           (0U)    ///< Position of GPIO_DB
#define GPIO_DB_Msk           (0xFFFFFFFFUL << GPIO_DB_Pos)   ///< Bitmask of GPIO_DB
/**
 * @def   GPIO_DB
 * @brief Configuration of debounce
 * <pre>
 * @a 1'b0 : Disable the debounce for each line
 * @a 1'b1 : Enable the function of debounce for each line
 * </pre>
 */
#define GPIO_DB               GPIO_DB_Msk

#define GPIO_DFG_Pos          (0U)    ///< Position of GPIO_DFG
#define GPIO_DFG_Msk          (0xFFFFFFFFUL << GPIO_DFG_Pos)    ///< Bitmask of GPIO_DFG
/**
 * @def   GPIO_DFG
 * @brief db_clk(used to define the glitc) configuration
 * <pre>
 * @a 32'h00000000 : db_clk will be pclk
 * @a Other values : db_clk will be gpio_dfg+1
 * No effect on de-bounce when gpio_db is 0.
 * </pre>
 */
#define GPIO_DFG              GPIO_DFG_Msk

#define GPIO_IG_Pos           (0U)    ///< Position of GPIO_IG
#define GPIO_IG_Msk           (0xFFFFFFFFUL << GPIO_IG_Pos)   ///< Bitmask of GPIO_IG
/**
 * @def   GPIO_IG
 * @brief Determines the interrupt group for 32 GPIO pins, each bit represents one GPIO pin
 * <pre>
 * @a 1'b0 : be associated with intr[0]
 * @a 1'b1 : be associated with intr[1]
 * </pre>
 */
#define GPIO_IG               GPIO_IG_Msk

/** @} GPIO_BITMAP */

/**
 * @addtogroup Exported_Macros
 * @{
 */

/**
 * @def   IS_GPIO_INSTANCE
 * @brief Check if INSTANCE is GPIO instance
 */
#define IS_GPIO_INSTANCE(INSTANCE)          ((INSTANCE) == GPIO)

/** @} Exported_Macros */

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* GT98XX_DEVICE_GT9881_GPIO_H_ */
